Low Power Verification Lead
Overview
- Added in 30 days
- 38
- At this company, still open
Skills named in this posting
- Place and route
- DFT
- Low-power design (UPF)
- Python
- Perl
As a Low Power Verification Lead, you will play a key role in ensuring low-power intent integrity across the design lifecycle. You will be responsible for VCLP signoff, ensuring seamless convergence between RTL, synthesis, and physical design stages for hierarchical designs.
Key Responsibilities
● Understand low power specs and write UPF for hierarchical designs
● Validate low-power architecture, UPF constraints, and intent across multiple domains.
● Debug VCLP failures, including issues arising from clock gating, retention, isolation, and level
shifters
● Ensure convergence of UPF across synthesis, place-and-route, and ECO cycles
● Work closely with RTL, Synthesis, DFT, and Physical Design teams to resolve low power
issues
● Develop automation scripts and improve methodology for VCLP sign-off
Technical Skills
● Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related discipline
● 7+ years of experience in low power methodologies and low power static verification using
VCLP
● Strong understanding of low-power design concepts (UPF) and methodologies
● Experience with synthesis, netlist optimizations, and equivalence debugging
● Proficiency in scripting languages such as TCL, Python, or Perl
● Experience with hierarchical Sub system level VCLP flows
Preferred Qualifications
● Familiarity with DFT concepts and scan impact on UPF and UPF checks
● Knowledge of STA and Physical Design interactions impacting UPF
Success in This Role Looks Like
● Clean VCLP sign-off
● Fast turnaround time in debugging and resolving VCLP/UPF issues
● Robust, scalable VCLP methodologies across projects
● Strong cross-team collaboration ensuring smooth design convergence
Why Semidynamics?
● Work at one of Europe’s most promising deep-tech semiconductor start up - from silicon to systems - Semidynamics.
● Accelerated development path.
● 4 days per week in the Barcelona office (city center), 1 day WFH.
● 1 week of work from everywhere in the world.
● Competitive package.
● A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.
Apply on the employer's site
Original posting: careers.semidynamics.com
RISC-V ecosystem
Semidynamics Technology Services, S.L. in the RISC-V ecosystem
RISC-V International: Strategic
Semidynamics is a supplier of high bandwidth RISC-V IP cores. | Semidynamics is a fabless semiconductor company based in Barcelona, focused on advancing high-performance AI inference through next-generation processor technology.
- Semidynamics designs fully customisable RISC-V processor IP (64-bit cores with wide vector units) in Barcelona
- Launched Cervell, a scalable RISC-V NPU for AI workloads, positioning itself as "AI with RISC-V"
- Ships a RISC-V SDK with ONNX Runtime support so AI models run on its cores
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