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Silicon Validation Engineer

Lyte AI

Sunnyvale, CASoC / ASICPosted Oct 20, 2026
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Skills named in this posting

  • Mixed-signal
  • Python
  • Perl
About the role • We are seeking a hands-on Validation Engineer to take our custom silicon devices from first power-on to production readiness. Embedded in a cross-functional team spanning analog design, logic design and package design, you will own bringup, debug, and end-to-end characterization bridging design intent and real-world silicon behavior. What you'll do • Lead silicon bringup for new silicon tape-outs – first power-on through functional validation • Develop and execute structured test plans covering functional, electrical, and performance validation • Characterize analog and digital circuit behavior against the product spec • Build automated test infrastructure using Python/Perl for high-throughput characterization • Debug complex mixed-signal devices – power, clocking, mixed-signal interfaces using oscilloscopes, logic analyzers, spectrum analyzers, and protocol analyzers • Validate high-speed interfaces including signal integrity analysis • Root-cause issues; distinguish design vs. process vs. board-level failures Required Qualifications • BS, MS, or PhD in Electrical Engineering from a top research university • 2–8 years of hands-on chip or system bringup and validation experience • Proficiency in Python or Perl for test automation and data analysis • Experience validating high-speed serial interfaces • Understanding of analog fundamentals such signal integrity, transmission lines, feedback theory, and voltage/current source compliance testing • Understand frequency domain and time-domain measurements and correlations • Solid analog circuit knowledge: bias networks, LDOs, PLLs, ADCs/DACs, and mixed signal interfaces – and the hands-on instincts to debug them at the bench • Ability to read and interpret schematics, layout files, and datasheet specs Preferred Qualifications • PVT corner characterization and yield analysis experience • Prior experience taping out a custom ASIC from prototype to production • Reliability testing exposure: HTOL, ELFR, ESD/latch-up Benefits (subject to location and local regulations) • Competitive salary and equity • Comprehensive medical, dental, and vision coverage • 401(k) retirement plan • Flexible vacation and time-off policy • Collaborative, fast-paced, and inclusive work environment • Opportunity to work on cutting-edge technologies with a highly cross-functional team

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Original posting: ats.rippling.com

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RISC-V ecosystem

Lyte AI in the RISC-V ecosystem

Perception layer for physical AI · AI · US · founded 2021

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