← Back to roles

Staff Engineer - MLSoC Design Verification and Silicon Validation (AI2496)

SiMa.ai

Bengaluru, IndiaRTL / HDLVerificationFirmwareSoC / ASICPosted Oct 20, 2026
Apply on SiMa.ai

Overview

Open roles
28
At this company
See all

Skills named in this posting

  • SystemVerilog
  • UVM
  • Microarchitecture
  • C
  • C++
  • Python
Description Job Title: Staff Engineer - MLSoC Design Verification and Silicon Validation Job Location: Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India Office) Job ID: AI2496 Job Description: The Design Verification (DV) engineer at SiMa is involved in the functional verification of blocks, sub-system and MLSoC. The Silicon Validation engineer at SiMa is involved in the silicon bring-up, silicon functional validation, debug and engineering support for SiMa.ai’s MLSoC™. Job Description As the MLSoC verification Engineer, you will • Build good understanding of SiMa MLSoC architecture. • Participate in assigned block’s architecture, micro-architecture, feature discussions and reviews. • Define and develop block and subsystem test bench components using UVM & System Verilog. • Bring up and test block functionality at block, subsystem and full-chip test environment. • Develop and execute a test plan, code coverage reviews and closure. • Manage debug of test and regression failures. • Work closely with the Architecture, MLSoC Hardware and MLA Software teams. As the MLSoC silicon Validation Engineer, you will • Develop silicon bring-up plans, development of post silicon validation content using SoC SW and automation. • Validation plan execution to validate the MLSoC functionality and performance measurements. • Work closely with the MlSoC Hardware, Boards, Software and Application teams. • Develop scope, boards automation for MLSoC power measurements. Required Background: • BS/MS in EE (Electrical Engineering) with 6+ years of experience in functional verification AND/OR silicon bring-up and silicon validation. • Very good experience of UVM and SystemVerilog based verification methodology is a must. • Experience with lab set-up, bring-up, silicon debug and silicon validation strategy and methodology are a plus. • Proficiency in C/C++ programming, Bare Metal O.S development, Python scripting is a plus • Good debug and problem solving skills. Personal attributes: Can-do attitude. Strong team player. Curious and good at solving problems. Execution and results oriented. Self-driven, Good communication skills.

Apply on the employer's site

Original posting: jobs.jobvite.com

Apply on SiMa.ai

RISC-V ecosystem

SiMa.ai in the RISC-V ecosystem

AI processing for edge devices · AI · US · founded 2018

Same employer

View all 28