Engineer/Sr. Engineer of Design Implementation

• Responsible for SDC and UPF/CPF development and debug. • Focus on design floor planning, power planning, IO planning, placement & CTS and routing, handling timing and congestion issue during project implementation. • IP level and chip level physical verification and DFM rule checking. • Power analysis and IR drop/EM analysis for both static and dynamic. • Strong capability in timing analysis, and independently handle all timing issues from netlist/RTL to GDS process. • Responsible for timing signoff for all functional modes and concerns, and work closely with DFT engineer for scan modes timing closure. • Work closely with package team and IO team regarding IO placement to address IO ESD, SSO and chip power supplement concerns. • Communicate with customer as well as AE or sales.