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Senior Signal/Power Integrity Engineer

Lyte AI

Sunnyvale, CASoC / ASICPosted Oct 20, 2026
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Skills named in this posting

  • Mixed-signal
  • PCIe
  • DDR / HBM
  • Ethernet
  • C++
  • Python
About the role • We are seeking Senior Level PCB Signal/Power Integrity Engineer to own and execute high-speed Signal Integrity (SI) and Power Distribution Network (PDN) simulations and validation. What you'll do • Collaborate with multi-disciplinary engineers (EE, System and Package) to define electrical performance related to SI, PI, EMI and EMC • Develop engineering test plans and methodologies for SI and PI simulation, including modelling of power networks, parasitic, impedance-controlled transmission lines, vias, connectors, sockets, and system components. • Validate power and signal integrity in laboratory settings, ensuring alignment with design specifications and simulation outcomes. • Analyze simulation and lab data to identify design issues and propose corrective actions. • Ability to support multiple projects concurrently, ensuring timely completion of design and validation tasks. Required Qualifications • Bachelor's degree in Electrical Engineering, or related field with at least 8 years of experience • Proficiency with Ansys SIwave, Ansys HFSS, Altium 365, Cadence Sigrity, and Keysight ADS • Experience design in of complex SoCs, PMICs, mixed-signal analog/digital designs for sensors and high-speed interfaces such as LPDDR4/4x, MIPI, 10G Ethernet and PCIe Gen 2/3 • Experience with system-level timing, loss budget including silicon, package and board impairments • Experience with lab measurements, debugging, and SI correlations using oscilloscopes, spectrum analyzer, VNA and TDR • Fluent in English communication, able to collaborate with teammates in different time zones • Ability to travel internationally as needed • Maintain company confidential information are a must Preferred Qualifications • Master’s degree with more experience is highly desired • Proactive member of the multi-disciplinary team, takes ownership of technical challenges and work with others to resolve issues • Nice to have experience in substrate design and packaging technology • Familiar with some of the device packaging processes such as die attach, flip chip, and wire bonding. • Data analysis experience such as JMPs is a plus; Excel is OK. • Programming and software maintenance skills are desired e.g. python, or C++ Benefits (subject to location and local regulations) • Competitive salary and equity • Comprehensive medical, dental, and vision coverage • 401(k) retirement plan • Flexible vacation and time-off policy • Collaborative, fast-paced, and inclusive work environment • Opportunity to work on cutting-edge technologies with a highly cross-functional team

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Original posting: ats.rippling.com

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RISC-V ecosystem

Lyte AI in the RISC-V ecosystem

Perception layer for physical AI · AI · US · founded 2021

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