Technology-driven logic synthesis for emerging transistor technologies

Logic synthesis turns a design into gates with cost models that were written for the technologies of the past: a cell costs what its library entry says, and the structure of the circuit below the gate is invisible to the tool. Emerging transistor architectures change what is cheap and what is expensive at the circuit level, and emerging workloads change which logic structures matter. A synthesis flow that cannot see either leaves most of the technology's potential on the table. The student will work on synthesis flows that bring technology awareness into the loop: physically grounded cost models for logic at the transistor and cell level, their use inside technology mapping and optimisation with open synthesis tools, and an evaluation on benchmark designs that shows how much a technology-aware flow gains over a conventional one and where the gains come from. Type of internship : Master internship Duration : 6-9 months Required educational background : Computer Science, Electrotechnics/Electrical Engineering Supervising scientist(s) : For further information or for application, please contact Siva Satyendra Sahoo ( SivaSatyendra.Sahoo@imec.be ) The reference code for this position is 2026-INT-357 . Mention this reference code in your application. Imec allowance will be provided for students studying at a non-Belgian university. Applications should include the following information: resume motivation current study Incomplete applications will not be considered