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芯片中端设计工程师8298

Unisoc (Shanghai) Technologies Co., Ltd.

上海市RTL / HDLPosted Aug 20, 2026
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Overview

Unisoc (Shanghai) Technologies Co., Ltd.
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Skills named in this posting

  • Verilog
  • STA
  • DFT
  • Low-power design (UPF)
  • Python
  • Tcl
  • Perl
1、承担项目中SOC中端流程建设与执行，包含RTL to Netlist的实现流程与相关质量检查流程。 2、支援Synthesis / DFT (MBIST SCAN) / LEC / CLP / STA / Timing ECO /Power ECO 相关流程的自主平台开发。 3、参与项目DFT / Clock / SDC / UPF 等架构规划及设计； 4、解决中端基于block level和fullchip level的前/后端流程交付问题 1、通信、电子、计算机等相关专业硕士及以上学历，3年以上行业相关工作经验； 2、熟练掌握Verilog语言 3，具备Tcl / Perl / python等相关脚本开发经验优先； 4、熟练掌握SOC前端流程，熟悉Synopsys / Cadence 主要EDA tool相关使用方法和flow； 5、具备子系统集成，流程自动化建设等验者优先； 6、具备良好的沟通能力和团队合作精神。

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Original posting: wecruit.hotjob.cn

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RISC-V ecosystem

Unisoc (Shanghai) Technologies Co., Ltd. in the RISC-V ecosystem

RISC-V International: Strategic

Unisoc, formerly Spreadtrum Communications, Inc., Unisoc has research centres in Shanghai, Beijing, Tianjin, Suzhou, Hangzhou, Chengdu, Xiamen, United States, Finland and India, technical support…

  • Unisoc (Shanghai) is a large Chinese mobile/IoT chipset vendor listed as a RISC-V member
  • Appears in RISC-V ecosystem coverage including a RISC-V ISA based DSP heading to mass production and RISC-V blockchain SIG activity

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