Application-Driven Memory xTCO

Current memory systems and hierarchies are struggling to keep pace with modern workload demands, especially those imposed by generative AI models. On-chip, SRAM scaling has stagnated due to physical scaling limits in advanced fabrication nodes. Meanwhile, off-chip, DRAM scaling is slowing due to challenges in layout and connectivity. As a result, novel memory technologies must be considered wholistically, both in terms of the technology proposition and the application-driven use case. imec works to identify and evaluate novel memory technologies, organizations, integrations, and packaging, including but not limited to string memories such as charge-coupled device memories (CCD), flash memories, embedded DRAM, ferro-backed memory, and others. On the Technology-Application Co-Optimization for Systems (TACOS) team, we specialize in end-to-end exploration of these memories and alternatives, i.e. from technology to application mapping, by using system-technology co-optimization (STCO) methodologies. This internship proposes the exploration of such memories from a co-design point of view, including both top-down (establishing technology requirements) and bottom-up (establishing application paradigm shifts) approaches. During this internship the candidate will be responsible for, Guided research of current and emerging memory technologies as well as interfacing in-house experts. Employing STCO methodology by way of using and connecting mixed-fidelity modelling and simulation tools. This can include analytical models, cycle-aware/-approximate simulation (with tools such as Ramulator, DRAMsys, or gem5), and/or cycle accurate simulation. Profiling and mapping applications with full- and sub-system awareness for technology propositions to quantify costs and trade-offs of data movement. Developing runtime optimisation strategies (e.g., adaptive tiling/scheduling and prefetching) to dynamically balance latency, bandwidth, and energy under changing workload phases. This role is ideal for someone who is deeply interested in hardware-software-technology codesign, memory architecture, and working in an interdisciplinary environment that values innovation, creativity, and real-world impact. Profile: You are analytical and detail-oriented, with a strong interest in technology, subsystem-level modelling and hardware-software codesign. You are adept at or have a keen interest in technology modelling, performance and energy analysis tools, and cutting-edge memory research. Type of internship : PhD internship, Master internship Duration : 6-12 months Required educational background : Electromechanical engineering, Computer Science, Electrotechnics/Electrical Engineering University promotor : Chris Van Hoof (KU Leuven) Supervising scientist(s) : For further information or for application, please contact Joshua Klein ( Joshua.Klein@imec.be ) The reference code for this position is 2026-INT-297 . Mention this reference code in your application. Imec allowance will be provided. Applications should include the following information: resume motivation current study Incomplete applications will not be considered