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Senior Power Engineer

NVIDIA Corporation

Israel, YokneamSoC / ASICPosted Jul 23, 2026
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Skills named in this posting

  • Ethernet
  • Python
Our team in Yokneam, Israel is looking for a Senior Power Integrity Engineer to join the Hardware Board Design team and lead PI development of next-generation Network Adapters for high-speed communication products. NVIDIA’s Networking division delivers end-to-end InfiniBand and Ethernet connectivity for servers and storage, including adapter cards, switches, cables and software that power data centers, cloud, big data, Web 2.0 and high-performance computing workloads. What you'll be doing: • Lead PI definition and implementation for board-level designs, from concept and architecture through validation, qualification and release to production. • Define the power core architecture and requirements and serve as the technical lead for all power-related performance and debug activities • Work closely with power supply vendors to align solutions with NVIDIA product needs, and build and optimize configuration files for programmable regulators. • Own power delivery network (PDN) design for complex network adapter boards, including rail partitioning, decoupling strategy, VR selection and dynamic load support. • Perform system-level power integrity simulations (frequency and time domain) and co-simulation of circuits and PDN models to predict noise. • Create and maintain board PI design guidelines: stackup, materials, breakout, routing, decoupling and placement rules for layout teams and external partners. • Use advanced 2D/3D EM tools to model and optimize vias, planes, connectors, sockets and other interconnect elements for power integrity. • Perform lab characterization and correlation using VNA, TDR and high‑bandwidth oscilloscopes; refine models and design rules based on measurement data. What we need to see: • B.Sc. in Electrical Engineering (or equivalent experience). • 5+ years of industry experience in signal and/or power integrity for high-speed board or system designs. • Strong understanding of electromagnetics, transmission line theory, PDN behavior and their application. • Expert-level proficiency with EM and PI tools (for example, Ansys HFSS/Q3D/SIwave, CST, or equivalent) and SPICE-based time-domain simulations. • Proven experience in PDN analysis, including model generation, impedance targets, resonance mitigation and time-domain noise simulations. • Hands-on lab experience with VNA, TDR and oscilloscopes for PI/SI validation, de-embedding and model correlation. • Ability to work independently in an intense, multi-disciplinary environment with strong ownership and excellent interpersonal skills. Ways to stand out from the crowd: • Deep experience designing PDNs for complex multilayer boards with high-current, low-voltage rails supporting advanced networking or compute ASICs. • Demonstrated background in PI co-simulation flows, PSIJ analysis and end-to-end system modeling (die–package–board). • Experience with scripting and data analysis using MATLAB, Python or C for simulation automation and large-signal data processing. • Exposure to advanced packaging and interconnect technologies (for example, TSV, high-speed connectors, advanced laminates). • Practical knowledge of PCB fabrication, product qualification flows and lab debug of complex high-speed boards. NVIDIA is widely considered to be one of the technology world’s most desirable employers, with some of the most talented and forward-thinking individuals working together on groundbreaking products and services. We are committed to fostering a diverse and inclusive work environment and are proud to be an equal opportunity employer that does not discriminate on any legally protected basis. If you are a creative and autonomous engineer with a real passion for power and signal integrity in cutting-edge networking systems, we want to hear from you.

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Original posting: jobs.nvidia.com

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Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.

  • NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
  • Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
  • Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage

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