Thermal Mitigation Strategies for Integrated Voltage Regulators in Advanced GPU Packages

Background The increasing power demand of artificial intelligence (AI) and high-performance computing (HPC) systems is driving the adoption of Integrated Voltage Regulators (IVRs) embedded directly within package substrates. By placing power conversion closer to the processor, IVRs improve power delivery efficiency and reduce electrical losses. However, the heat generated by these regulators introduces additional thermal loads within the package, potentially increasing GPU junction temperatures and reducing overall system performance. As future AI accelerators move towards multi-kilowatt power levels, understanding and mitigating the thermal impact of embedded IVRs is becoming a critical design challenge. Emerging package architectures are exploring double-sided cooling and alternative heat extraction paths through the package backside, but their effectiveness and design trade-offs remain insufficiently understood. Objective The objective of this thesis is to investigate the thermal coupling between embedded IVRs and GPUs and develop thermal mitigation strategies for next-generation AI and HPC packages through advanced thermal modelling and simulation. Research Scope The student will develop detailed thermal models of advanced GPU packages containing embedded IVRs and evaluate the influence of IVR power dissipation on package and GPU temperatures. The work will focus on: Quantifying the thermal impact of embedded IVRs on GPU hotspot and junction temperatures. Understanding heat flow paths and thermal coupling mechanisms between IVRs and compute dies. Investigating the effectiveness of double-sided cooling architectures. Exploring alternative heat extraction paths toward the package backside through thermal vias, heat spreaders, and high-conductivity materials. Performing parametric studies on IVR location, substrate properties, package stack-up, and cooling configurations. Generating design guidelines for thermally optimized integration of power delivery in advanced packages. Methodology The research will primarily rely on finite-element simulations using state-of-the-art modeling tools. Thermal resistance breakdowns, temperature distributions, and heat-flow analyses will be used to evaluate various package architectures and cooling concepts. Design trade-offs between thermal performance, package complexity, and implementation feasibility will be assessed. Expected Outcomes The thesis will deliver: Thermal modelling framework for GPU packages with embedded IVRs. Quantitative assessment of the thermal penalty introduced by embedded power delivery. Comparative evaluation of single-sided and double-sided cooling approaches. Identification of critical thermal pathways and bottlenecks. Design recommendations for future AI and HPC package architectures incorporating embedded voltage regulation. Candidate Profile The project is suitable for Master students in Mechanical Engineering, Applied Physics or Electromechanical Engineering with an interest in thermal management, semiconductor packaging, and numerical simulation. Thermal modelling or finite element theory experience is required. Type of internship : Master internship Duration : 1 year Required educational background : Mechanical Engineering, Electromechanical engineering University promotor : Houman Zahedmanesh (KU Leuven) Supervising scientist(s) : For further information or for application, please contact Onur Yenigun ( Onur.Yenigun@imec.be ) The reference code for this position is 2026-INT-304 . Mention this reference code in your application. Only for self-supporting students. Applications should include the following information: resume motivation current study Incomplete applications will not be considered