Modelling, analysis and design of an ADPLL in 22nm"

Modern communication systems performance is greatly impacted by the timing accuracy of the frequency synthesizers that clock them. Chip-to-chip interconnections quality often requires the synthesizers to be co-integrated with the clocked system, typically a data converter, meaning that having digital-intensive solutions that are mostly technology-agnostic has a lot of value in the development of a complex system. For this kind of mixed-signal systems, accurate modelling and verification against simulation is crucial, and will be the focus of the work in the implementation of an All-Digital Phase-Locked-Loop (ADPLL). Type of internship : Master internship Duration : 6 months Required educational background : Electrotechnics/Electrical Engineering Supervising scientist(s) : For further information or for application, please contact Angelo Parisi ( Angelo.Parisi@imec.be ) The reference code for this position is 2026-INT-271 . Mention this reference code in your application. Imec allowance will be provided for students studying at a non-Belgian university. Applications should include the following information: resume motivation current study Incomplete applications will not be considered