Synthesis Engineer

Focus areas include but are not limited to: synthesis, STA, timing closure, place & route and/or sign-off. Prospective team members require strong Verilog/SystemVerilog; STA expertise; SDC; synthesis/STA tools preferred. Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day remote. Policy may change. DROP US YOUR LINKEDIN PROFILE OR CV Other Openings • Processor Design Engineer • Verification Engineer • Synthesis Engineer • Compiler Engineer (SIMT) • Compiler Engineer (P&R Heuristics) • Software Engineer (Tooling) • Embedded Software Engineer (Bare-Metal) • Embedded Systems Software Engineer (OS and Bare-Metal)