Synthesis Engineer
RTL / HDLVerificationCompilersPhysical designPosted Aug 16, 2026
Overview
Skills named in this posting
- SystemVerilog
- Verilog
- STA
- Place and route
Focus areas include but are not limited to: synthesis, STA, timing closure, place & route and/or sign-off.
Prospective team members require strong Verilog/SystemVerilog; STA expertise; SDC; synthesis/STA tools preferred.
Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role.
Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.
DROP US YOUR LINKEDIN PROFILE OR CV
Other Openings
• Senior Software Engineer (Processor Software Stack)
• Verification Engineer
• Synthesis Engineer
• Compiler Engineer (P&R Heuristics)
Apply on the employer's site
Original posting: ubitium.com
RISC-V ecosystem
Ubitium in the RISC-V ecosystem
RISC-V International: Strategic Start-Up
Ubitium develops a universal RISC V microprocessor designed to replace conventional processors, enabling the execution of any code, algorithm, or application for seamless and efficient computing…
- Ubitium is building a "universal" RISC-V processor that handles CPU, GPU, DSP and FPGA-style workloads on one general-purpose RISC-V datapath
- Debuted as enabling AI "at no additional cost" while raising $3.7M seed funding
- Featured in RISC-V International's newsletter (December 2024) as a new RISC-V silicon startup
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