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Bachelor/ Master Thesis - Implementation of a Latch-Based Register File for RISC-V Cores (f/m/div)

Infineon Technologies AG

MunichRISC-VRTL / HDLVerificationPosted Aug 31, 2026
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Skills named in this posting

  • Verilog
  • VHDL
  • DFT
  • Microarchitecture
  • Python
#WeAreIn to create tiny chips and big careers. The future won’t wait... why should you? Join us and make a difference. Whether you join as a student, intern, or trainee, you'll be part of something real - real projects, real impact, and real opportunities to grow. Are you in? Your role Key responsibilities in your new role • Build your technical foundation: Get familiar with Infineon’s code generation framework, RISC-V processor architectures, and register-file implementations • Develop latch-based register-file solutions: Investigate latch-based storage architectures and clocking schemes for processor register files, then develop and implement a configurable latch-based register-file solution • Evaluate implementation options: Assess different implementation options with respect to timing, area, power, and robustness • Analyze design-for-testability: Analyze DFT aspects and compare latch-based and flip-flop based approaches • Integrate your work: Integrate the solution into the code-generation framework and generate implementations for various RISC-V cores • Verify and validate: Perform functional verification, synthesis, and implementation studies • Contribute to research: Contribution to a publication is desired Your profile Qualifications and skills to help you succeed • Education: Bachelor's or master's student in Computer Science, Electrical Engineering, or similar • Interests: Bring a background in design, synthesis, timing analysis, and simulation of digital circuits using (System-)Verilog or VHDL • Knowledge: Have an understanding of digital design concepts such as latches, flip-flops, clock gating, and DFT • Skills: Proficiency in Python, Linux, and Git; programming skills are a must • Experience: Ideally, have experience with processor microarchitecture and RISC-V • Availability: You are available for an upfront internship to get familiar with some of techniques before the thesis starts • Language skills: Fluent English skills, both written and spoken; German is a plus Please attach the following documents to your application: • CV in English • Certificate of enrollment at university • Excerpt of the study regulations for the thesis (if applicable) • Latest grades transcript (not older than 6 months) • High school report #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon. Recruiter: Britta Johansson

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Original posting: jobs.infineon.com

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RISC-V ecosystem

Infineon Technologies AG in the RISC-V ecosystem

RISC-V International: Premier Board

Infineon Technologies AG is a German semiconductor manufacturer founded in 1999, when the semiconductor operations of the parent company Siemens AG were spun off.

  • Brought RISC-V to automotive: first to announce an automotive RISC-V microcontroller family
  • Showed a virtual prototype/virtual automotive RISC-V chip with Synopsys for early software development

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