CPU设计工程师
Shanghai StarFive Semiconductor Co., Ltd.
北京、上海、成都RTL / HDLPhysical designPosted Oct 20, 2026
Overview
Skills named in this posting
- SystemVerilog
岗位职责：
1.负责CPU具体模块的电路设计，比如执行单元；
2.配合DV做好功能的收敛；
3.与架构组协同工作负责微架构的迭代，优化PPA能够达到设计要求。
任职要求：
1.熟练掌握RTL代码书写，精通system verilog等HDL语言；
2.掌握必要的EDA工具，以及熟练运用Linux环境与脚本完成必要的开发工作；
3.对计算机体系结构基本必要的理解，尤其对于基本的CPU的流水线，以及乱序执行等基本结构；
4.能够团队协作，有效配合DV和架构的debug以及ppa迭代的工作；
5.有主观能动性、愿意思考，态度认真，并敢于钻研，对于困难问题敢于迎头而上。
Apply on the employer's site
Original posting: starfivetech.com
RISC-V ecosystem
Shanghai StarFive Semiconductor Co., Ltd. in the RISC-V ecosystem
RISC-V International: Strategic
StarFive is a world-leading provider of RISC-V chips and solutions.
- StarFive designs RISC-V application SoCs and the boards built on them
- Its JH7110 RISC-V SoC powers the VisionFive / VisionFive 2 single-board computers, among the most widely used RISC-V Linux SBCs
- Actively upstreams Linux support (e.g. its camera subsystem driver landed in Linux 6.8) and integrates third-party IP such as VeriSilicon's display processor
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