← Back to roles

ASIC Infrastructure/ Digital Design Engineer

Synopsys

Bengaluru, IndiaSoC / ASICPosted Nov 8, 2026
Apply on Synopsys

Overview

Open roles
405
At this company
See all
Added in 30 days
255
At this company, still open

Skills named in this posting

  • Python
  • Tcl
  • Perl
Date posted 11/07/2026 Category Engineering Hire Type Employee Job ID 19317 Date Posted 11/07/2026 We Are: Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP integration, simulation and analysis solutions and design services., empowering the creation of high-performance silicon chips and software content. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are: You’re an early-career engineer eager to build semiconductor design infrastructure. You value rigorous digital design and enjoy improving tool flows as much as writing code. You understand that when a designer’s environment breaks, productivity drops and milestones slip—and you care. You think in systems, not just scripts, considering dependencies, data ownership, and failure modes before automating. You can debug Linux, Python, and EDA issues independently, knowing when a workaround is acceptable versus when to fix the root cause. You take initiative, ask questions, read documentation, and test safely before deploying changes. You are keen on improving productivity of design flow using latest available AI tools and methodology. At Synopsys, you’ll keep ASIC teams productive and accelerate silicon IP delivery. What You'll Be Doing: • Develop and maintain infrastructure supporting daily ASIC design, verification, test and implementation workflows. • Install, configure, upgrade, and manage EDA tools and licenses (simulation, synthesis, timing, etc.). • Build and maintain automation for flow setup, job submission, tracking, data management, and reporting (Python/Tcl/Bash/Perl). • Support compute and storage platforms: filesystem management, monitoring, and ensuring capacity/availability for large datasets. • Support HPC/compute farms and schedulers: batch submissions, resource allocation, and job scheduling. • Troubleshoot and proactively monitor environments (tool configs, permissions, paths, licenses), and maintain clear documentation for users. • Work with the central methodology teams to test, deploy new design flows. Use AI tools/flow to improve the execution efficiency. The Impact You Will Have: • Keep ASIC design teams productive and on track for tapeout by ensuring infrastructure uptime and stability. • Automate repetitive setup and flow tasks to save engineers significant time each week. • Proactively monitor compute, storage, and licenses to prevent issues from blocking critical runs. • Ensure compute farm and storage capacity scales smoothly during simulation/synthesis workload spikes. • Deliver reliable updates, documentation, and self-serve processes that reduce troubleshooting and prevent downstream failures. What You'll Need: • Bachelor's or Master's in Computer Science, Electrical Engineering, Electronics Engineering, or equivalent practical experience. • 0-2 years of experience in software development, scripting, IT infrastructure, or engineering support roles. • Proficiency in at least one scripting language such as Python, Tcl, Bash, or Perl. • Working knowledge of Linux operating systems and command-line tools. • Ability to read technical materials, follow procedures, and learn new tools independently. • Exposure to ASIC design flows, EDA tools, or semiconductor engineering environments is a plus. • Familiarity with compute farms, HPC environments, or large-scale storage systems is a plus. • Experience with configuration management or release processes is a plus. • Some experience of AI tools/flow is an added plus. Who You Are: • Proactive problem solver, comfortable with ambiguity and rapid change. • R&D mindset engineer someone who can troubleshoot issues end-to-end by reproducing failures, checking logs, and isolating tool vs. environment vs. user causes. • Collaborative team player who communicates clearly with engineers, explaining problems like license failures without blame. • Problem solver. Writes robust automation with logging and error handling to handle real-world usage and edge cases. • Detail-oriented and highly organized. Creates clear, beginner-friendly documentation that enables self-service and consistent execution. Stays organized and proactive: track tasks, provide status updates, and escalate blockers early to keep workflows reliable. The Team You'll Be Part Of You will join a team at Synopsys that builds and supports the infrastructure powering daily ASIC design and verification. You’ll collaborate with CAD/IT and R&D IP engineering teams to maintain EDA tool environments, automation, compute farms, and storage systems. The team values strong troubleshooting, clear documentation, and safe change management to keep workflows stable and teams on track for tapeout. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Apply on the employer's site

Original posting: careers.synopsys.com

Apply on Synopsys

RISC-V ecosystem

Synopsys in the RISC-V ecosystem

Synopsys makes chip design software and processor IP, including ARC-V RISC-V cores. It acquired Intrinsic ID in 2024.

  • Security-IP (PUF/authentication) supplier active in the RISC-V ecosystem, incl. RISC-V Foundation showcases at Embedded World
  • Associated with RISC-V side-channel mitigation research (XDIVINSA instruction diversification)

Same employer

View all 405