[NanoIC topic] Admittance modeling for scoping defects in advanced germanium Metal-Oxide-Semiconductor gate stacks for CFET

CMOS scaling is entering the 3D era with complementary field-effect transistors (CFETs), in which n- and p-type devices are vertically stacked on top of eachother reducing the standard-cell footprint and improving transistor density without relying solely on further lateral pitch reduction. Germanium (Ge) is particularly attractive for the p-channel device because its high hole mobility can increase drive current and energy efficiency, making Ge-based CFET integration a potential enabler of higher-performance, more compact logic. However, Ge gate stacks remain highly sensitive to interface states and border traps, which can degrade mobility, shift threshold voltage, increase variability, and compromise reliability, particularly Bias Temperature Instability (BTI). Physics-based defect modeling used to correctly interpret widely collected frequency- and temperature-dependent admittance measurements vs. bias, is essential to identify the relevant defect populations, extract their energetic and kinetic properties, link them to materials and processing, and guide the optimization of robust germanium gate stacks for manufacturable CFET technology. The first part of the internship will focus on developing an admittance model, implementing it in Comphy, our in-house device simulator, and using it to fit experimental data. The model can be introduced in stages of increasing complexity, starting from the essential physics and progressively incorporating parasitic and secondary effects, including series resistance, defect-assisted minority-carrier generation, surface-potential fluctuations, and temperature dependencies. The second part of the internship will apply the model to real-world experimental datasets to evaluate whether the fitting approach performs reliably in practice. Based on the observed agreement, stability, and parameter sensitivity, the model and fitting methodology will be iteratively refined, including the fitting strategy, parameter constraints, and treatment of measurement artefacts, to achieve the most accurate, robust, and physically meaningful extraction possible. We offer an interdisciplinary research environment that brings together world-leading expertise in semiconductor devices, materials, characterization, and physics-based modeling. The intern will work in imec’s state-of-the-art laboratory environment and gain exposure to research conducted in close collaboration with the world’s leading semiconductor companies, providing a unique opportunity to contribute to technology developments with direct industrial relevance. Type of internship : Master internship, PhD internship Duration : minimum 6 months Required educational background : Electrotechnics/Electrical Engineering, Nanoscience & Nanotechnology, Physics, Materials Engineering Supervising scientist(s) : For further information or for application, please contact Dieter Claes ( Dieter.Claes@imec.be ) and Koen Martens ( Koen.Martens@imec.be ) The reference code for this position is 2026-INT-291 . Mention this reference code in your application. Imec allowance will be provided for students studying at a non-Belgian university. Applications should include the following information: resume motivation current study Incomplete applications will not be considered