Reliability of 3D advanced technologies: the hybrid-bonding interface.
Overview
Join imec, one of the world’s premier
research centers in nanotechnology, at its headquarters in Leuven, Belgium, to
study the reliability of the most advanced 3D technology: wafer to wafer
hybrid-bonding. Understanding the reliability of the SiCN wafer-to-wafer
interface is key in assessing the reliability of this technology. As the traditional more Moore approach is
slowing down, due to the increase in development costs and logic complexity, 3D
technologies are enabling complex More than Moore Systems-on-Chip (SoC),
offering higher performances and functionalities to customers. 3D SoC combine
efficiently chips from different technology nodes through vertical
interconnections, enabling complex designs out of reach of the monolithic approach.
Vertical interconnection technologies are therefore key enablers of the More
than Moore paradigm, allowing higher densities with reduced latencies. In
particular, wafer-to-wafer hybrid bonding will be key to the success of the
next generation of 3D Systems-on-Chip by bringing the interconnect densities
above 10 6 mm −2 . Wafer to wafer hybrid bonding connects two
fully processed wafers with compatible die sizes through copper pads and a
bonding dielectric, which, at imec, is SiCN (shown in Fig. 1). Unfortunately,
this novel technology comes along with key reliability challenges. The constant
pitch down-scaling results in an increased leakage current along the bonding
interface which can be further enhanced by pad-to-pad misalignment. While this
misalignment can be mitigated with imec unequal pad schemes, the resulting
copper-dielectric interface could lead to metal ion drift at elevated
temperature and electric fields. The study aims to characterize the intrinsic
reliability of various SiCN dielectric materials as potential candidates for
the bonding interface. A special emphasis will be placed on understanding the
impact of the dielectric composition on the defect generation rate and on the
nature of the defects. The following activities are foreseen: SiCN
reliability data will be collected using various methodologies (constant
voltage/current stresses, interrupted/uninterrupted stress) at high and low
temperatures to trigger dielectric degradation. Data
preparation and data analyses will be performed by the student . Finally,
a lifetime model will be developed to estimate the maximum use voltage and
temperature for various mission profiles. Type of internship : Master internship Duration : 4-6 months Required educational background : Materials Engineering, Physics Supervising scientist(s) : For further information or for application, please contact Emmanuel Chery ( Emmanuel.Chery@imec.be ) The reference code for this position is 2026-INT-274 . Mention this reference code in your application. Only for self-supporting students. Applications should include the following information: resume motivation current study Incomplete applications will not be considered
Apply on the employer's site
Original posting: imec-int.com
RISC-V ecosystem
imec in the RISC-V ecosystem
RISC-V International: Community
Interuniversity Microelectronics Centre is an international research & development organization, active in the fields of nanoelectronics and digital technologies.
- RISC-V research/design: system-level integration of a digital AI accelerator with RISC-V
- Participates in RISC-V automotive and space-chip ecosystem work
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