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Engineer/Sr. Engineer of SoC FE Flow

VeriSilicon, Inc.

ShanghaiRTL / HDLSoC / ASICPosted Jul 9, 2019
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Overview

VeriSilicon, Inc.
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Skills named in this posting

  • STA
  • DFT
• Comprehend the SoC clock structure and working mode and prepare the SDC file for SoC design. • Prepare the DFT plan for the SoC design. • SCAN/MBIST/BSD insertion and synthesize methodology for Flatten / Hierarchical design. • Pre/Post simulation for test patterns. • Cooperate with timing engineer for timing signoff (STA). • Analog IP test implementation and simulation. • Support ATE engineer for chip testing debug, and analyze ATE log file to locate root cause of failure. Formal check of RTL and netlist.

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Original posting: verisilicon.com

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RISC-V ecosystem

VeriSilicon, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

VeriSilicon is a Silicon Platform as a Service company that provides world class SoC and SiP solutions and a leading IP provider with IP portfolios address markets including mobile internet devices, datacenters, the Internet of Things (IoT), automotive, industrial, and medical electronics.

  • VeriSilicon supplies the GPU, ISP and display IP that RISC-V SoCs integrate, plus custom silicon services
  • Its display processor IP was adopted in StarFive's RISC-V based JH-7110 vision platform
  • Canaan's RISC-V edge AIoT SoC adopted VeriSilicon ISP and GPU IPs, and its embedded GPU IP powers HPMicro's HPM6800 RISC-V MCU series

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