Early-Stage Thermal Screening Methodology for Advanced HBM–GPU Integration

Context Advanced HBM–GPU integration is a key enabler for next-generation AI systems, yet thermal constraints remain a primary limiter. imec has recently demonstrated system-technology co-optimization approaches to mitigate thermal bottlenecks in advanced HBM–GPU concepts under realistic power conditions. However, early-stage design decisions are still often dominated by expensive, slow iteration cycles. There is a strong need for fast, data-driven screening methodologies that can translate power dissipation signatures into actionable guidance on which integration solutions should be prioritized for detailed analysis. Objective Develop a portable methodology and prototype toolchain that leverages power-map analytics to enable early-stage screening and prioritization of candidate advanced integration solutions. The internship focuses on building robust, architecture-consistent power-map descriptors and a scoring workflow that supports design-space exploration under limited information. Key responsibilities Power-map processing pipeline (Python-first) Build a reproducible pipeline to ingest, normalize, re-bin, and analyze workload-derived power maps; support multiple map formats and resolutions. Feature engineering for power-map “fingerprints” Define and implement multi-scale spatial descriptors capturing power concentration, heterogeneity, clustering behavior, and structural regularities in a way that is robust across workloads and mapping conventions. Architecture-consistent synthetic power-map generation Create synthetic power-map variants that remain consistent with computer-architecture realities (e.g., clustered activity, compute/memory locality, floorplan constraints), to stress-test methodology robustness and generalization. Screening score and decision workflow Propose a scoring framework that can rank candidate integration solutions using power-map fingerprints and limited configuration metadata, with emphasis on stability, interpretability, and sensitivity analysis. Validation and reporting Validate the screening workflow against a small set of reference cases and produce a concise report summarizing methodology, robustness, and recommended usage boundaries. Optional stretch goal Explore generative data augmentation (e.g., GAN-style synthesis) to enrich the space of architecture-consistent power maps for robustness testing (kept optional and scoped to feasibility). Candidate profile MSc or early PhD student in Electrical/Computer Engineering, Computer Architecture, or related fields. Strong hands-on programming skills; Python required (NumPy/Pandas; bonus: SciPy/scikit-learn). Solid understanding of computer architecture and workload behavior (power distribution drivers, compute/memory interaction). Comfortable with building end-to-end research prototypes: data processing, metrics design, benchmarking, and clear documentation. Interest in thermal/power topics and advanced packaging is a plus, but the internship is primarily methodology- and tooling-driven. What you will deliver A clean and reproducible Python toolchain for power-map analytics and screening. A documented set of power-map fingerprints and a screening score. A short technical report including robustness analysis and recommended best practices for using the methodology in early-stage exploration. Reference: https://www.imec-int.com/en/press/imec-mitigates-thermal-bottleneck-3d-hbm-gpu-architectures-using-system-technology-co https://www.imec-int.com/en/expertise/cmos-advanced-and-beyond/xtco Chen, Y., Lofrano, M., Moolchandani, D., Oprins, H., Van Der Plas, G., Ryckaert, J., Biswas, D. and Myers, J., 2025, December. Breaking Thermal Bottleneck in 3D HBM-on-GPU Integration via System-Technology Co-Optimization. In 2025 IEEE International Electron Devices Meeting (IEDM) (pp. 1-4). IEEE. https://ieeexplore.ieee.org/abstract/document/11353711 Environment: You will work in imec’s highly interdisciplinary research environment, at the intersection of system technology co-optimization (STCO), power and thermal modeling, memory and architecture research, and EDA methodology development. The internship is embedded in imec’s XTCO program thermal pillar, where architectural, physical, and system-level considerations are jointly explored to address next-generation compute challenges. You will collaborate closely with researchers across power/thermal modeling, memory integration, system architecture, and EDA tooling, and gain exposure to realistic industrial design constraints, data, and workflows. The work is hands-on and methodology-driven, with a strong emphasis on building reusable analysis pipelines rather than isolated simulations. Daily advisors: Yukai Chen, Matthew Walker Type of internship : Master internship, PhD internship Duration : 6-12 Months Required educational background : Electrotechnics/Electrical Engineering, Computer Science Supervising scientist(s) : For further information or for application, please contact Yukai Chen ( Yukai.Chen@imec.be ) The reference code for this position is 2026-INT-140 . Mention this reference code in your application. Imec allowance will be provided. Applications should include the following information: resume motivation current study Incomplete applications will not be considered