Product Engineering Architect
Cadence Design Systems, Inc.
NOIDAPhysical design2026-09-21
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168 results · page 4 of 7 · dates: UTC
Technical Director, Digital Design Methodology & Flow Architecture
NXP Semiconductors Netherlands B.V.
Austin (Oakhill, Office)RTL / HDLPhysical design2026-09-20Design Verification Architect / Director
Cadence Design Systems, Inc.
SAN JOSERTL / HDLVerification2026-09-20STAGE- Architectures de pompes de charge et boucles de régulation - F/H
STMicroelectronics International N.V.
France2026-09-17Staff System Architecture and Design Engineer
Analog Devices, Inc.
US, CA, San Jose, Rio RoblesRTL / HDLFirmwareFPGA2026-09-17- TaipeiVerificationSoC / ASIC2026-09-17
Midcore Design Verification Engineer
Tenstorrent
Santa Clara, California, United States; SpainRISC-VRTL / HDLVerificationCompilers2026-09-16Sr-Staff Performance Engineer
Qualcomm Technologies, Inc.
Austin, Texas, United States of AmericaKernel / LinuxFirmwareSoC / ASIC2026-09-16Front End Design Verification Engineer
Tenstorrent
Santa Clara, California, United States; SpainRISC-VRTL / HDLVerificationCompilers2026-09-15Datacenter Product Architect
NVIDIA Corporation
US, CA, Santa Clara2026-09-152027 PhD SerDes Optical Transceivers Silicon Design and Architecture Modeling Engineer Intern/Co-op
Advanced Micro Devices (AMD)
San Jose, California; Santa Clara, CaliforniaRTL / HDL2026-09-11CDI - Imager SoC & Digital architect - F/H
STMicroelectronics International N.V.
Grenoble, FranceFirmwareSoC / ASIC2026-09-11Physical Design CPU Methodology Engineer
Tenstorrent
Santa Clara, California, United StatesRISC-VRTL / HDLCompilersPhysical design2026-09-10- HsinChu2026-09-07
Principal Engineer, Digital IC Design and Architecture
Analog Devices, Inc.
US, OR, BeavertonRTL / HDLVerificationPhysical design2026-09-06Senior System Design Test Architect
NVIDIA Corporation
Israel, Yokneam2026-09-03- Irvine, CAVerification2026-08-31
CPU Micro-architect/RTL Designer (Multiple Locations)
Qualcomm Technologies, Inc.
Austin, Texas, United States of America, Santa Clara, California, United States of AmericaRTL / HDLVerificationPhysical design2026-08-30- New York, NY2026-08-30
Postdoctoral Fellowship at Design++
ETH Zurich
100%, Zurich, fixed-term2026-08-28- San JoseVerification2026-08-27
Staff CPU/NPU Architecture RTL Design Engineer
Qualcomm Technologies, Inc.
Markham, Ontario, CanadaRISC-VRTL / HDLPhysical designSoC / ASIC2026-08-27- Ditzingen, GermanySecurity2026-08-27
- RTL / HDLVerificationFirmwareSoC / ASIC2026-08-27
3D Memory Chip Architect and Design, Principal Engineer
Qualcomm Technologies, Inc.
San Diego, California, United States of AmericaRTL / HDLPhysical designSoC / ASIC2026-08-26
