Principal Engineer, Design Verification Engineering
Analog Devices, Inc.
India, Bangalore, RMZRISC-VRTL / HDLVerificationFirmware2026-09-23
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Analog Mixed-Signal IC Design Engineer – Data Converters (ADC/DAC), Staff - Cambridge, UK
Qualcomm Technologies, Inc.
Cambridge, United KingdomRTL / HDLPhysical designSoC / ASIC2026-09-23FPGA prototyping/FPGA design Engineer (Lead/Staff)
Qualcomm Technologies, Inc.
Bangalore, IndiaFPGA2026-09-23CPU RTL Design Engineer (Senior/Staff) - Cambridge, UK
Qualcomm Technologies, Inc.
Cambridge, United KingdomRTL / HDLVerificationPhysical designSoC / ASIC2026-09-23Server CPU Clock Physical Design Engineer, Staff level - Cambridge, UK
Qualcomm Technologies, Inc.
Cambridge, United KingdomRTL / HDLFirmwarePhysical designSoC / ASIC2026-09-23GPU Design Verification Engineer - Qualcomm, Cambridge, United Kingdom
Qualcomm Technologies, Inc.
Cambridge, United KingdomRTL / HDLVerificationCompilersKernel / Linux2026-09-23CPU Design Verification Engineer (Senior level) - Cambridge, UK
Qualcomm Technologies, Inc.
Cambridge, United KingdomVerificationFirmwarePhysical designSoC / ASIC2026-09-23Senior SRAM Engineer, Circuit Design
NVIDIA Corporation
US, CA, Santa ClaraVerificationPhysical design2026-09-23Senior ASIC Design Engineer
NVIDIA Corporation
US, CA, Santa ClaraRTL / HDLPhysical designSoC / ASIC2026-09-23- Grugliasco, Torino, ItalyFPGA2026-09-23
- Austin, TexasRTL / HDLCompilersPhysical designSoC / ASIC2026-09-23
Senior CPU Design Engineer
10xEngineers
2026-09-23Senior CPU Design Verification Engineer
10xEngineers
Verification2026-09-23Design Verification Intern
Quadric.io
Burlingame, CA (HQ)RTL / HDLVerificationFirmware2026-09-22Hardware and Software Design Intern
STMicroelectronics International N.V.
Santa Clara, United StatesFirmware2026-09-22Lead Design Verification Engineer-Memory Controller
Advanced Micro Devices (AMD)
San Jose, CaliforniaRTL / HDLVerificationSoC / ASIC2026-09-22Physical Design Engineer, Timing
Tenstorrent
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United StatesRISC-VCompilersPhysical design2026-09-22- San Jose, CACompilersPhysical designSoC / ASIC2026-09-22
Design Engineer - Die-to-Die Interface
MediaTek Inc
HsinChuFirmwarePhysical designSoC / ASIC2026-09-22- HsinChuVerification2026-09-22
Sr. Staff Memory Design Engineer
MediaTek Inc
San Jose, CAPhysical designSoC / ASIC2026-09-22[MSL/SPD5] Senior/Staff Physical Design Engineer
MediaTek Inc
SingaporeRTL / HDLPhysical designSoC / ASIC2026-09-22RTL Design Engineer – Power Design
Advanced Micro Devices (AMD)
Austin, TexasRTL / HDLSoC / ASIC2026-09-22CPU Architecture and RTL Design Engineer
Advanced Micro Devices (AMD)
Dublin, IrelandRTL / HDLPhysical design2026-09-22Lead Physical Design Engineer
Advanced Micro Devices (AMD)
Santa Clara, CaliforniaRTL / HDLVerificationCompilersPhysical design2026-09-22
