Principal Product Engineer - Verification
Cadence Design Systems, Inc.
GYEONGGI-DO (Seoul)Verification2026-10-27
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Senior Design Verification Engineer (IP)
Lattice Semiconductor Corporation
Penang, MalaysiaRTL / HDLVerificationFPGA2026-10-26Senior Chip Design Verification Engineer
NVIDIA Corporation
Israel, Tel AvivRTL / HDLVerificationFirmwareSoC / ASIC2026-10-26MSIP Design Verification Engineer - Cork, Ireland
Qualcomm Technologies, Inc.
Cork, IrelandRTL / HDLVerificationPhysical designSoC / ASIC2026-10-26- Austin, Texas, United States of America, Santa Clara, California, United States of AmericaRISC-VRTL / HDLVerificationSoC / ASIC2026-10-24
Digital Electronics Principal Verification Engineer
Cadence Design Systems, Inc.
EDINBURGH 01RTL / HDLVerificationSoC / ASIC2026-10-23Senior Principal Engineer, SoC Design Verification
MIPS Tech LLC.
Hyderabad, Telangāna, IndiaRISC-VRTL / HDLVerificationFirmware2026-10-23- Da Nang, VietnamRTL / HDLVerificationSoC / ASICFPGA2026-10-23
Associate Design Verification Engineer
Analog Devices, Inc.
Philippines, Cavite, GTCRTL / HDLVerification2026-10-22NPU Design Verification Engineer (Multiple Levels)
Qualcomm Technologies, Inc.
San Diego, California, United States of AmericaRTL / HDLVerification2026-10-22Senior Design Verification Engineer
Lattice Semiconductor Corporation
Manila, PhilippinesRTL / HDLVerificationSoC / ASICFPGA2026-10-20- San Jose, CaliforniaRTL / HDLVerificationSoC / ASIC2026-10-20
ASIC Verification Engineer
RaiderChip
On-Site (Solares, Spain) • Full-timeRequirements: • Develop and execute comprehensive verification strategies for ASIC designs • Create simulation environments to aggressively validate functionality • Leverage existing FPGA-proven designs as reference and validation baseline • Strong experience with RTL simulation and verification methodologies • Working experience with Synopsys toolsVerificationSoC / ASIC2026-10-20FPGA Engineer (Prototyping)
RaiderChip
On-Site (Solares, Spain) • Full-timeRequirements: • Use FPGA emulation to stress, debug, and validate ASIC-designs • Leverage long-running, proven FPGA prototypes as functional reference • Validate functionality through SW simulation and HW emulation • Collaborate closely with ASIC frontend and verification engineers • Drive issue detection, root-cause analysis, and fix validation • Strong experience with RTL simulation and FPGA toolchains (AMD/Xilinx)FPGA2026-10-20- Hsinchu, Hsinchu County, TaiwanRISC-VRTL / HDLVerificationFirmware2026-10-20
Design Verification Engineer H/F
Arteris IP
RTL / HDLVerificationCompilersSoC / ASIC2026-10-20Design Verification Engineer H/F
Arteris IP
RTL / HDLVerificationCompilersSoC / ASIC2026-10-20Principal Design Verification Engineer
Arteris IP
Biot, FranceRTL / HDLVerificationSoC / ASIC2026-10-20Principal Formal Design Verification Engineer
Microsoft Corporation
India, Karnataka, BangaloreRTL / HDLVerificationSoC / ASIC2026-10-15- Hsinchu, TaiwanRTL / HDLVerificationFirmwareSoC / ASIC2026-10-15
- Noida, IndiaRTL / HDLVerificationSoC / ASIC2026-10-15
Video IP Design Verification Engineer
Qualcomm Technologies, Inc.
Bangalore, IndiaRTL / HDLVerificationPhysical designSoC / ASIC2026-10-14Turing Design Verification Principal Manager
Qualcomm Technologies, Inc.
Noida, Uttar Pradesh, IndiaVerificationFPGA2026-10-13Senior Chip Design Verification Engineer
NVIDIA Corporation
Israel, Yokneam, Israel, Tel AvivRTL / HDLVerificationFirmwareSoC / ASIC2026-10-13- Bengaluru, Karnataka, IndiaRISC-VRTL / HDLVerificationSoC / ASIC2026-10-09
