Senior Layout Design Engineer
Synopsys
Noida, IndiaPhysical design2026-10-28
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67 results · page 1 of 3 · dates: UTC
- Dresden, DE (primary site)2026-10-27
Mask Layout Designer
Advanced Micro Devices (AMD)
California, United States2026-10-26Layout Design, Staff Engineer
Synopsys
Seongnam-si, South KoreaRTL / HDLCompilersFirmware2026-10-26Senior Package Layout Engineer - Hardware
NVIDIA Corporation
India, BengaluruSoC / ASIC2026-10-24Package Layout Design Staff/Senior Staff Engineer
Marvell Asia PTE Ltd
BangalorePhysical designSoC / ASIC2026-10-22Staff Layout & Design Automation Engineer
Analog Devices, Inc.
Spain, Valencia, Cortes ValencianasPhysical design2026-10-21Engineer Analog Layout Design
Infineon Technologies AG
Ho Chi Minh CityPhysical design2026-10-21Staff Engineer Layout Design
Infineon Technologies AG
Shanghai, 上海2026-10-16Senior Package Layout Engineer - Hardware
NVIDIA Corporation
India, BengaluruSoC / ASIC2026-10-16- Hanoi, VietnamPhysical design2026-10-15
Design Engineer II – Memory Layout
Signoff Semiconductors Inc.
Bangalore2026-10-14Layout Design Engineer
Xsight Labs
Armenia, YerevanCompilersPhysical design2026-10-13Layout Design, Staff Engineer
Synopsys
Bengaluru, IndiaCompilersPhysical designSoC / ASIC2026-10-13Senior IC Layout design Engineer
Advanced Micro Devices (AMD)
San Jose, CaliforniaPhysical design2026-10-08- Bengaluru, IndiaVerificationPhysical designSoC / ASIC2026-10-07
Staff Engineer Layout and Mask Design
Infineon Technologies AG
Bangalore BTPPhysical design2026-10-06Senior Mask Layout Design Engineer
NVIDIA Corporation
Taiwan, Hsinchu, Taiwan, TaipeiPhysical designSoC / ASIC2026-10-06Senior Mask Layout Design Engineer
NVIDIA Corporation
US, CA, Santa Clara, US, TX, AustinPhysical designSoC / ASIC2026-10-06Layout Design, Staff Engineer
Synopsys
Yerevan, ArmeniaCompilersSoC / ASIC2026-10-06Layout Design, Manager
Synopsys
Yerevan, ArmeniaCompilersPhysical design2026-10-06Layout Design Manager
Synopsys
Yerevan, ArmeniaPhysical design2026-10-03Senior SerDes & Analog Layout Design Engineer
Microsoft Corporation
United States, North Carolina, Raleigh, United States, Texas, Austin, United States, District of Columbia, Washington D.C., United States, Washington, Redmond, United States, Idaho, Boise, United States, Oregon, Hillsboro, United States, California, Mountain ViewPhysical designSoC / ASIC2026-10-01ECAD Layout Design Engineer
The Charles Stark Draper Laboratory, Inc.
Cambridge, MA2026-09-30Mixed Signal IC Layout Engineer
Tenstorrent
Santa Clara, California, United StatesRISC-VCompilersPhysical designSoC / ASIC2026-09-28
