ASIC Design Engineer, BOOT and Power Management
NVIDIA Corporation
India, Bengaluru, India, HyderabadRTL / HDLPhysical designSoC / ASIC2026-10-27
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Analog Mixed Signal/Power Management Design Engineer (Sr up to Staff)
Qualcomm Technologies, Inc.
San Diego, California, United States of AmericaRTL / HDLSoC / ASIC2026-10-27Analog Design Engineering Intern (Power Management)
Analog Devices, Inc.
United Kingdom, Edinburgh, SC, FreerVerificationPhysical design2026-10-20- RTL / HDL2026-10-20
Power Management Systems Design and Verification Engineer
Qualcomm Technologies, Inc.
San Diego, California, United States of AmericaVerificationFirmware2026-09-25- Cambridge, England, United KingdomRISC-VRTL / HDLVerificationPhysical design2026-09-22
- Austin, Texas, United StatesRISC-VRTL / HDLVerificationSoC / ASIC2026-09-22
Next Gen CPU Power Management RTL Design Engineer
Advanced Micro Devices (AMD)
Santa Clara, CaliforniaRTL / HDLFirmwarePhysical designSoC / ASIC2026-09-18- SingaporeVerificationPhysical designSoC / ASIC2026-08-24
Senior ASIC Power Management Micro Architect, Chip Design
NVIDIA Corporation
Israel, Yokneam, Israel, Tel AvivRTL / HDLPhysical designSoC / ASIC2026-08-20Staff Engineer - Power Management IC Design
Qualcomm Technologies, Inc.
Santa Clara, California, United States of AmericaRTL / HDL2026-08-17- Santa Clara, California, United StatesRISC-VRTL / HDLVerificationPhysical design2026-08-08
- Santa Clara, California, United StatesRISC-VRTL / HDLVerificationPhysical design2026-08-08
- Santa Clara, California, United StatesRISC-VRTL / HDLVerificationPhysical design2026-07-31
Power Management IC application Engineer
MediaTek Inc
HsinChu2025-04-18Power Management IC Design Engineer_HsinChu
MediaTek Inc
HsinChuSoC / ASIC2021-07-22
