Power Management IC (PMIC) Analog Design Engineer

Summary: We are looking for a Senior Power Management IC (PMIC) Analog Design Engineer to join our team. In this role, you will work on the architecture and design of high-performance analog and mixed-signal power chips. You will own complex blocks, drive chip execution, and mentor junior engineers. You will guide projects from early concept all the way to final mass production. Key Responsibilities • Lead architecture: Define top-level chip architectures for complex buck, boost, and buck-boost switching regulators. • Design advanced circuits: Design high-efficiency power stages, complex control loops, and high-precision sensors. • Own layout & verification: Guide layout teams, and ensure robust chip layout matches simulations. • Drive chip validation: Lead lab evaluation and silicon debug to solve complex chip issues on the bench. • Mentor teams: Teach and guide junior engineers through circuit design, layout, and debug strategies. • Support production: Work with test and product engineers to guarantee high yields in volume production Required Skills and Qualifications • Experience: 5+ years of hands-on experience in PMIC circuit design with a track record of successful tape-outs. • Education: Master's or Ph.D. degree in Electrical Engineering with a focus on power electronics or analog IC design. • Technical expertise: Knowledge of DCDC converters, advanced control topologies, and chip stability criteria. • Software mastery: Expert skills in Cadence Virtuoso, Spectre, and top-level chip verification tools. • Problem solving: Strong ability to debug complex silicon issues and isolate noise or reliability failures. Preferred Qualifications • Experience designing high-voltage or high-current systems. • Familiarity with advanced BCD (Bipolar-CMOS-DMOS) fabrication nodes. • Ability to model circuits using tools like Python, Matlab, or Verilog-A. Location: Prefer Santa Clara, CA