Develop and execute validation plans for HSI systems, such as PCIe, USB, DP, HDMI, UFS, CSI, and UCIe PHY. Design, implement, and maintain test benches and validation environments for system-level and interface-level testing. Perform signal
Semiconductor and RISC-V jobs in Hsinchu, Taiwan 283
Engineering roles in Hsinchu, Taiwan at 11 companies, collected from the employers' own careers pages. Every role links to the original posting.
Roles 271–283 of 283, newest first.
- HsinChuFirmwareJan 27, 2026
Senior ASIC Verification Engineer, Coherent High Speed Interconnect
NVIDIA Corporation
Taiwan, Hsinchu, Taiwan, TaipeiRTL / HDLVerificationSoC / ASICJan 26, 2026We are now looking for a ASIC Verification Engineer - Coherent High Speed Interconnect! For two decades, we have pioneered visual computing, the art and science of computer graphics. With our invention of the GPU - the engine of modern visu
Product Engineer
MediaTek Inc
HsinChuSoC / ASICJan 11, 20261. Participate in the development and deployment of ASIC and other products utilizing advanced process nodes. 2. Support the design, validation, and mass production introduction of new product lines and technologies such as CPO, IVR, cHBM,
Wafer Sourcing Project Manager
MediaTek Inc
HsinChuJan 11, 2026Responsible for wafer outsourcing , capacity management, and cost negotiation, including: 1.Competitive Price: RFQ, price negotiation, cost prediction, cost reduction initiatives, CA. 2.Capacity: long-term reservation, short-term fulfillmen
System Expert for Post-silicon
MediaTek Inc
HsinChuFirmwareJan 6, 2026• Key Development Technologies: System firmware development, high-speed physical layer data transmission software development, hardware performance optimization, and product quality control. • Main Objectives: Complete firmware development
Advanced Substrate/PCB technology Expert
MediaTek Inc
HsinChuJan 5, 20261. New SBT vendor bring up , New SBT vendor YIP , troubleshooting and Ops 2. 3D, 3.5D & e-IVR Technology Enabling, CPC/CPO technology building block development 3. Common strip format unification management 4. Advanced PCB Ultra-Large size.
Senior SerDes /System Engineer
MediaTek Inc
HsinChuVerificationFirmwareJan 1, 2026• Responsible for high-speed SerDes development, including firmware design and implementing algorithms, IC functional verification, system performance optimization, and customer support (familiar with architecture, firmware, debugging, opti
- HsinChuVerificationDec 30, 2025
1. Communication system analysis for 5G NR system (a) PHY Spec and Procedure Validation (b) Algorithm design verification and signal analysis (c) System verification and procedure analysis 2. Communication platform development for 5G NR sys
- HsinChuFirmwarePhysical designFPGADec 9, 2025
1. Own the top-level integration of internal and third-party IPs into SOC or FPGA platform. 2. Ensure interface compatibility, clock/reset domain correctness. Resolve integration issues including timing, CDC/RDC, and floorplan. 3. Work clos
Senior Signal and Power Integrity Engineer
MediaTek Inc
HsinChuDec 9, 2025We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and
Power related PCB Design Engineer
MediaTek Inc
HsinChuVerificationNov 27, 20251.PCB power related hardware design:Resonsible for design and develop hardware including circuit design, component evaluation and selection, customized component planning, layout review, etc. 2. System specification and design requirement c
CPU - Embedded Software Engineer
MediaTek Inc
HsinChuFirmwareNov 18, 2025CPU Embedded Software Engineer The ideal candidate will be responsible for developing and maintaining the embedded software stack for CPU/MCU subsystem. This role requires a deep understanding of CPU architecture, low-level system softwar
- HsinChuSoC / ASICNov 6, 2025
Join MediaTek's "DFT for Advanced Process Platform" team -- your work directly impacts Cloud ASIC reliability and yield at the most advanced process nodes (N4/N3/N2 and beyond). - DFT Architecture & Insertion: Define and implement Scan (ful