Design verification and validation — UVM, formal methods and testbench engineering.
Roles 2,221–2,247 of 2,247, newest first.
Atmosic
At Atmosic, we are re-architecting wireless connectivity solutions from the ground up to radically reduce IoT device dependence on batteries. We aim to make batteries last forever and the Internet of Things battery free – thus breaking the
Unisoc (Shanghai) Technologies Co., Ltd.
1、根据 IP 硬件加速器模块 Design SPEC 制定验证计划； 2、基于 UVM方法学独立搭建模块级验证平台； 3、协助 Designer 完成 Debug 相关工作，完成模块验证收敛以及验证Signoff； 4、协助完成 IP 在 SoC level 验证工作，达到 SoC level 验证收敛需求。 1、电子，通信或计算机硕士及以上学历； 2、5年以上相关工作经验，至少一次成功流片经验； 3、熟悉 ASIC 设计流程，对 UVM 验证方法学有较深的理解； 4、具
Unisoc (Shanghai) Technologies Co., Ltd.
1、负责高速/存储接口(USB/UFS/PCIE/LPDDR等)IP级或SOC系统级验证； 2、分析系统应用场景，制定详细验证计划（包括但不限于验证用例），组织计划评审；作为专家参与芯片设计文档的评审，输出有效意见； 3、规划验证架构和环境，并使用SV/UVM搭建验证环境或指导低级别工程师进行环境搭建和用例设计，熟练使用VIP(Testsuit)构建验证用例； 4、运行和调试验证用例或指导低级别工程师开展运行和调试工作，确保达成目标覆盖率，评审和签收验证的完整性。 1、2年
Unisoc (Shanghai) Technologies Co., Ltd.
1、负责高速/存储接口(USB/UFS/PCIE/LPDDR等)IP级或SOC系统级验证； 2、分析系统应用场景，制定详细验证计划（包括但不限于验证用例），组织计划评审；作为专家参与芯片设计文档的评审，输出有效意见； 3、规划验证架构和环境，并使用SV/UVM搭建验证环境或指导低级别工程师进行环境搭建和用例设计，熟练使用VIP(Testsuit)构建验证用例； 4、运行和调试验证用例或指导低级别工程师开展运行和调试工作，确保达成目标覆盖率，评审和签收验证的完整性。 1、2年
Unisoc (Shanghai) Technologies Co., Ltd.
1、根据SoC子系统Design SPEC 制定验证计划，进行 Bus/Clock/Low power/Performance（包括且不限于）等相关验证工作； 2、基于 UVM方法学独立搭建子系统级，并完成子系统级环境平滑迁移集成到SoC top level验证平台； 3、协助 Designer 完成 Debug 相关工作，完成子系统级验证收敛以及验证Signoff； 4、完成 power estimation 和 performance evaluation 相关开发仿真工
Unisoc (Shanghai) Technologies Co., Ltd.
1、开发用于IP，子系统或SOC级验证的DV测试平台； 2、制定验证计划，书写UVM代码，完善测试用例，分析代码覆盖率和功能覆盖率； 3、持FPGA测试和芯片测试。 1、通信、电子、计算机等相关专业本科以上学历； 2、熟悉System Verilog语法和UVM验证方法学，深入理解ASIC验证流程； 3、 熟悉ARM架构及AMBA总线协议； 4、具备良好的沟通能力和团队合作精神。
Unisoc (Shanghai) Technologies Co., Ltd.
1、负责高速/存储接口(USB/UFS/PCIE/LPDDR等)IP级或SOC系统级验证； 2、分析系统应用场景，制定详细验证计划（包括但不限于验证用例），组织计划评审；作为专家参与芯片设计文档的评审，输出有效意见 3、规划验证架构和环境，并使用SV/UVM搭建验证环境或指导低级别工程师进行环境搭建和用例设计，熟练使用VIP(Testsuit)构建验证用例； 4、运行和调试验证用例或指导低级别工程师开展运行和调试工作，确保达成目标覆盖率，评审和签收验证的完整性。 1、5年以
We are seeking highly motivated New Grad Digital Front-End Design Engineers to join our ASIC Design Services team in the United States. In this role, you will work on challenging customer projects across a wide range of applications, includ
Unisoc (Shanghai) Technologies Co., Ltd.
1. 负责高速/存储接口(USB/UFS/PCIE/LPDDR等)IP级或SOC系统级验证； 2. 分析系统应用场景，制定详细验证计划（包括但不限于验证用例），组织计划评审；作为专家参与芯片设计文档的评审，输出有效意见 3. 规划验证架构和环境，并使用SV/UVM搭建验证环境或指导低级别工程师进行环境搭建和用例设计，熟练使用VIP(Testsuit)构建验证用例； 4. 运行和调试验证用例或指导低级别工程师开展运行和调试工作，确保达成目标覆盖率，评审和签收验证的完整性； 1
Unisoc (Shanghai) Technologies Co., Ltd.
1. 负责高速/存储接口(USB/UFS/PCIE/LPDDR等)IP级或SOC系统级验证； 2. 分析系统应用场景，制定详细验证计划（包括但不限于验证用例），组织计划评审；作为专家参与芯片设计文档的评审，输出有效意见 3. 规划验证架构和环境，并使用SV/UVM搭建验证环境或指导低级别工程师进行环境搭建和用例设计，熟练使用VIP(Testsuit)构建验证用例； 4. 运行和调试验证用例或指导低级别工程师开展运行和调试工作，确保达成目标覆盖率，评审和签收验证的完整性； 1
VeriSilicon, Inc.
• Develop architecture modeling tools for RTL design and design verification. • Develop and validate test cases to verify accuracy and efficiency of modeling tools. • Design novel algorithms to solve computer vision and machine learning p
Senior Digital LC/MAC Designer Atmosic Technologies is looking for LC/MAC design engineers who are passionate about delivering differentiated low-power and battery-free wireless connectivity solutions. Job title and responsibilities commen
Atmosic Technologies is looking for a digital verification engineer who is passionate about delivering differentiated low-power and battery-free wireless connectivity solutions. Job title and responsibilities commensurate with experience.
Atmosic
Sr. Digital Design Engineer Atmosic is looking for a Sr. Digital Design Engineer who is passionate about delivering differentiated low-power and battery-free wireless connectivity solutions. You will provide technical leadership with prove
We are looking for an experienced digital verification engineer, who is capable of driving the required verification flows for our mixed-signal designs. The ability to work closely with rtl design team and the analog team, and to develop d
Senior Digital Design Engineer focusing on the digital datapath of high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include RTL design, verification, behavioral modelling, support and assist with syn
VeriSilicon, Inc.
• Design and implement new features in GPU architecture and C-Model. • Maintain existing GPU architecture and C-Model. • Evaluate and improve performance and quality of GPU architecture. • Design interface with driver. • Work with RTL team
• Validate pre-silicon system-on-chip (SoC) using FPGA (Field Programmable Gate Array) platform; • Perform silicon bring up and validation of SOC with radio transceivers; • Verify silicon and board-level functionality, as well as the over
VeriSilicon, Inc.
• Understanding the expected functionality of designs. • Developing testing and regression plans. • Designing and developing verification environment. • Running RTL and gate-level simulations/regression. • Code/functional coverage developme
VeriSilicon, Inc.
Focus on analog/digital mixed IP and Chip verification. The engineers need to act as a strong team member and contributor, who also need to collaborate with digital F.E team closely. • Understanding the expected functionality of designs. •
VeriSilicon, Inc.
• Develop environments for ZSP system functional verification. • Write verification plans for ZSP system level IPs and systems. • Develop verification environments for IP and systems using C, verilog, Assembly, SystemVerilog, etc. • Contrib
VeriSilicon, Inc.
• Understanding the expected functionality of designs. • Developing testing and regression plans. • Designing and developing verification environment. • Running RTL and gate-level simulations/regression. • Code/functional coverage developme
VeriSilicon, Inc.
• Capable of independently contributing to and working on the design/implementation/verification of passes of certain intermediate-language representation level of backend compiler for GPU/DSP targets. • Capable of designing/implementing op
VeriSilicon, Inc.
• Design and implement new features in GPU architecture and C-Model. • Maintain existing GPU architecture and C-Model. • Evaluate and improve performance and quality of GPU architecture. • Design interface with driver. • Work with RTL team
Analog/Mixed-Signal Verification Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include the verification of analog and mixed-signal designs for high performance data converters
MediaTek Inc
As deep sub-micron process requires longer research cycle and higher manufacture cost, DV(design verification) has become an inevitable part of design group in Mediatek chip development flow. CDG DV is in charge of development and implement
Job overview The Formal Verification Engineer independently executes formal verification activities for complex hardware designs, ensuring functional correctness, robustness, and quality before tape-out. The role involves developing and op
