Design verification and validation — UVM, formal methods and testbench engineering.
Roles 2,191–2,220 of 2,247, newest first.
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakth
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakth
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakth
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakth
1. Serdes IP FW and related algorithm design and development, including IP verification and system performance improvement, e.g. 50G/100G/200G/300G/400G. 2. Collaborate with analog/digital/algorithm teams to co-develop chips from prototype
Unisoc (Shanghai) Technologies Co., Ltd.
1、根据 IP 硬件加速器模块 Design SPEC 制定验证计划； 2、基于 UVM方法学独立搭建模块级验证平台； 3、协助 Designer 完成 Debug 相关工作，完成模块验证收敛以及验证Signoff； 4、协助完成 IP 在 SoC level 验证工作，达到 SoC level 验证收敛需求。 1、电子，通信或计算机硕士及以上学历； 2、5年以上相关工作经验，至少一次成功流片经验； 3、熟悉 ASIC 设计流程，对 UVM 验证方法学有较深的理解； 4、具
1. Serdes/High speed interface related PHYD IP architecture planning 2. Serdes/High speed interface related PHYD IP RTL coding 3. Serdes/High speed interface related PHYD IP front-end and back-end integration 4. Co-work with PCS/MAC design
Lanxin Computing
职位描述： 1、负责芯片的设计验证工作，实施验证计划的制定、验证平台搭建、激励生成和测试、覆盖率分析；实施和负责软硬件协同验证； 2、与设计人员一起debug设计缺陷，熟练理解验证模块，提高验证质量； 3、负责验证环境和流程的开发和维护。 职位要求： 1、电子、微电子、计算机等相关专业本科及以上学历，三年以上验证经验优先，有实际流片经验者优先； 2、熟悉芯片开发验证流程，熟练掌握UVM验证方法学，软硬件协同仿真； 3、精通SystemVerilog硬件描述和验证
Lanxin Computing
职位描述： 负责RISC-V架构的处理器内核验证。1、用Verilog/SystemVeriog，熟悉UVM验证方法学；2、用EDA编译、仿真、debug工具；3、搭建testbench，分析应用场景并构造case，以及回归和覆盖率收集以及报告分析。 职位要求： 候选人以下技能要求的优先考虑： 1、RISC-V架构处理器内核验证经验；2、NPU计算内核验证经验； 3、Cache验证经验，熟悉缓存一致性协议。
MediaTek Inc
• Develop and maintain digital HW IP • Perform IP verification with DV and SW team • Security HW IP design • Verification HW IP on FPGA • Perform front-end integration jobs (synthesis, SCAN, TMBIST, Code Coverage...) #LI-LL1
Unisoc (Shanghai) Technologies Co., Ltd.
工作职责 1.根据SoC子系统Design SPEC 制定验证计划，进行 Bus/Clock/Low power/Performance（包括且不限于）等相关验证工作； 2.基于 UVM方法学独立搭建子系统级，并完成子系统级环境平滑迁移集成到SoC top level验证平台； 3.协助 Designer 完成 Debug 相关工作，完成子系统级验证收敛以及验证Signoff； 4.完成 power estimation 和 performance evaluation 相关
Unisoc (Shanghai) Technologies Co., Ltd.
1.负责WCN IP验证，包括WiFi/BT/GNSS/FM。 2.理解WiFi/BT/GNSS/FM协议。 3.使用System Verilog/UVM搭建验证环境，完成UT/BT/IT/ST验证。 4.支持FPGA测试和芯片测试。 1.熟悉System Verilog和UVM。 2.深入理解ASIC设计流程，熟悉ARM架构及AMBA总线协议。 3.熟悉WiFi/BT/GNSS/FM协议，熟悉通信系统者优先。 4.有脚本基础（Perl/Python/Shell/Tcl均可
Silicon Assurance
Position Description: We are looking for creative, growth minded, team oriented, and highly motivated full-time/part-time offensive security researcher who can consistently deliver high-quality work in a fast-paced environment of technology
Silicon Assurance
Position Description: We are looking for creative, growth minded, team oriented, and highly motivated full-time Director of SW Engineering who can consistently deliver high-quality work in a fast-paced environment of technology startup. You
Unisoc (Shanghai) Technologies Co., Ltd.
1、负责WCN IP验证，包括WiFi/BT/GNSS/FM 2、理解WiFi/BT/GNSS/FM协议 3、使用System Verilog/UVM搭建验证环境，完成UT/BT/IT/ST验证 4、支持FPGA测试和芯片测试 1、熟悉System Verilog和UVM。 2、深入理解ASIC设计流程，熟悉ARM架构及AMBA总线协议。 3、熟悉WiFi/BT/GNSS/FM协议，熟悉通信系统者优先。 4、有脚本基础（Perl/Python/Shell/Tcl均可）者优先
Unisoc (Shanghai) Technologies Co., Ltd.
1. 负责WCN IP验证，包括WiFi/BT/GNSS/FM 2. 理解WiFi/BT/GNSS/FM协议 3. 使用System Verilog/UVM搭建验证环境，完成UT/BT/IT/ST验证 4. 支持FPGA测试和芯片测试 1. 熟悉System Verilog和UVM 2. 深入理解ASIC设计流程，熟悉ARM架构及AMBA总线协议 3. 熟悉WiFi/BT/GNSS/FM协议，熟悉通信系统者优先 4. 有脚本基础（Perl/Python/Shell/Tcl均
無線通訊設計驗證 包含 Test plan 規劃, Bench, VIP 建立, test case 撰寫, 完成coverage等相關驗証工作 #LI-LL1
Mobileye Vision Technologies Ltd.
The Mobileye Automated Driving Hardware group in Haifa is looking for an Experienced Formal Verification Engineer to join a team of talented engineers developing next-generation silicon for autonomous driving platforms. This is a unique opp
Renesas RISC-V 32 & 64-Bit MCUs and MPUs
Job Description • Extract verification objectives from specification and review them with our team • Define the verification strategy/plan and execute it • Develop test benches and verification components • Define and implement test scenar
What MatX Is Building MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking silicon verification engineers to join our
Unisoc (Shanghai) Technologies Co., Ltd.
1、参与IP设计验证，主要涉及摄像/音视频/显示等领域，具有多媒体背景的优先； 2、参与需求分析, 设计讨论，性能评估，模块/链路等功能和性能验证； 3、负责IP验证方案、验证计划和验证报告的编写，完成评审检视和验收，确保IP高质量交付； 4、 使用SV/UVM搭建验证环境，并构造完备性用例，确保达成目标覆盖率。 1、2年以上数字芯片验证经验，熟悉数字电路基础知识； 2、微电子/电子/通信/计算机/自动化/信息等相关专业，硕士及以上学历； 3、熟悉Verilog/Syste
Unisoc (Shanghai) Technologies Co., Ltd.
1、参与IP设计验证，主要涉及摄像/音视频/显示等领域，具有多媒体背景的优先； 2、参与需求分析, 设计讨论，性能评估，模块/链路等功能和性能验证； 3、负责IP验证方案、验证计划和验证报告的编写，完成评审检视和验收，确保IP高质量交付； 4、 使用SV/UVM搭建验证环境，并构造完备性用例，确保达成目标覆盖率。 1、2年以上数字芯片验证经验，熟悉数字电路基础知识； 2、微电子/电子/通信/计算机/自动化/信息等相关专业，硕士及以上学历； 3、熟悉Verilog/Syste
Unisoc (Shanghai) Technologies Co., Ltd.
1、参与IP设计验证，主要涉及摄像/音视频/显示等领域，具有多媒体背景的优先； 2、参与需求分析, 设计讨论，性能评估，模块/链路等功能和性能验证； 3、负责IP验证方案、验证计划和验证报告的编写，完成评审检视和验收，确保IP高质量交付； 4、 使用SV/UVM搭建验证环境，并构造完备性用例，确保达成目标覆盖率。 1、2年以上数字芯片验证经验，熟悉数字电路基础知识； 2、微电子/电子/通信/计算机/自动化/信息等相关专业，硕士及以上学历； 3、熟悉Verilog/Syste
1. IEEE 802.3 Ethernet PHY & transceiver architecture & algorithm design 2. Digital signal processing of mixed-signal design 3. System simulation/model design for pre-silicon verification 4. System & algorithm design/simulation of high-spee
Develop and review test plans Develop verification environment/testbench in Module/IP/SOC level Develop verification IP and reference model Implement test with randomization based coverage driven verification methodology Implement functiona
Renesas RISC-V 32 & 64-Bit MCUs and MPUs
Job Description • Extract verification objectives from specification and review them with our team • Define the verification strategy/plan and execute it • Develop test benches and verification components • Define and implement test scenar
MediaTek Inc
Key Qualifications • Preferably BE/B.Tech/ME/M.Tech in EEE/ECE/CSE with 5-12 years of relevant industry experience. • Should have experience in verification methodology. • Architecting and development of testbench, test-bench components for
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakth
Renesas RISC-V 32 & 64-Bit MCUs and MPUs
Job Description The Role • Conception and definition of innovative and efficient test strategies for our mixed-signal ICs in close collaboration with our design teams and Design for Test Department • Design and development of both softwar
