Formal Verification Engineer

Job overview The Formal Verification Engineer independently executes formal verification activities for complex hardware designs, ensuring functional correctness, robustness, and quality before tape-out. The role involves developing and optimizing properties, running advanced formal verification techniques, mentoring junior engineers, and collaborating closely with design teams to achieve verification closure. Responsibilities: • Develop and maintain formal verification environments, writing assertions to validate RTL designs against specifications. • Run formal analysis to identify bugs and corner-case issues, with guidance on complex scenarios. • Debug counterexamples and collaborate with design and verification teams to resolve issues. • Contribute to equivalence checking, verification planning, and coverage closure activities. • Support improvements to verification flows, automation, and documentation while building expertise in formal methodologies. Requirements: Education Bachelors/Masters/Doctorate in EEE/ECE/CS/Maths/Physics Technical Skills: Linux/Unix Verilog/ SystemVerilog /VHDL Digital design Open-source projects in design/verification RISC-V/Arm/x86/MIPS SVA/PSL/Theorem proving Tcl/Python/Bash Soft Skills Problem solving Ownership Autonomy Team spirit Attention to detail Language skills: English Experience: 2-3 years of relevant design/verification experience 1-2 years of FV experience at least 1 project experience where autonomously run small scale projects (<2 months) Right to work We provide sponsorship for exceptional candidates, upon conditional terms and conditions. In Return: You’ll apply your formal verification expertise to technologies that shape and support millions of devices for years to come. This role gives you the opportunity to step into a field where you can grow your technical leadership and impact.