Domain & Validation Engineer
RTL / HDLFPGAPosted Oct 20, 2026
Overview
- Added in 30 days
- 32
- At this company, still open
Skills named in this posting
- PCIe
Domain & Validation Engineer
Location: Penang, Malaysia
Responsibilities:
• Provide technical expertise to resolve customer’s design issue.
• Develop reference design to demonstrate FPGA usage.
• Assist other development and operation teams in performing hardware/IP issues debug and analysis.
• Perform FPGA hardware system validation and potentially logic simulation.
• Provide technical information and data on Efinix products to internal and external users.
• Generate product collaterals including datasheet, technical notes and application notes.
• Design and develop FPGA development kits for new FPGA devices
• Working closely with FAE and Solutions AE (SAE) in providing a solution to ease customer’s adoption to Efinix’s products.
• Ensure timely response to FAE/SAE for customers technical support requests.
• Participate in periodic Supplier assessment to evaluate suppliers’ performance.
• Perform tasks needed by company which adhere to company policy to ensure company’s business operation.
Qualifications:
• Bachelor/Masters Degree in Electrical/Electronics Engineering.
• Experience in FPGA design tools and implementation.
• Strong problem solving and analytical skill.
• Strong in RTL and system knowledge or understanding.
• Candidate with basic knowledge in DDR/MIPI/PCIe will be an added advantage.
• Good communication skills.
• Self-motivated team player and willing to work as a team.
• Highly motivated to learn and adapt to fast-changing technologies and environment.
Apply on the employer's site
Original posting: efinixinc.com
RISC-V ecosystem
Efinix Inc in the RISC-V ecosystem
RISC-V International: Strategic
Our mission is to drive the future of edge computing w/our Trion® FPGA silicon platform.
- FPGA vendor promoting RISC-V SoCs on its devices ("RISC-V SoCs: Powering Embedded Computing")
- RISC-V soft cores used across its Trion/Titanium FPGA product lines
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