DFT Engineer
RTL / HDLSoC / ASICFPGAPosted Oct 20, 2026
Overview
- Added in 30 days
- 32
- At this company, still open
Skills named in this posting
- DFT
- Mixed-signal
- Python
- Perl
DFT Engineer
Location: Penang, Malaysia
Responsibilities:
• Define and developing comprehensive DFT strategy and architectures for all FPGA chips including its digital, analog and mixed-signal blocks.
• Work with Design team in implement and verifying the DFT structures (scan, BIST, JTAG, ATPG and etc) to ensure the structures are correctly inserted in FPGA products.
• Support DFT pattern generation, verification, test coverage analysis and improvement for FPGA’s IP/system.
• Lead the tradeoff of test coverage vs. test cost evaluation and decision making to ensure high coverage while achieving cost target for each product.
• Support post-silicon bring-up, yield analysis/improvement, silicon debug of DFT pattern issues on bench/ATE to root cause the problem.
• Develop DFT flow automation to improve efficiency and reduce manual effort.
Qualifications:
• BS or MS in Electrical/Electronic/Computer Engineering with min 5 years’ experience in DFT development.
• Solid knowledge in different DFT scheme and architecture, scan, ATPG, MBIST, JTAG, boundary scan, at-speed testing and etc.
• Experience in creating and implementing complex chip-level DFT architecture.
• Knowledge of defect types, fault models, debugging, and validation on ATE and silicon bring-up.
• Prior experience in engaging Design teams on pre-Silicon test planning and validation.
• Strong understanding of design principles and the full ASIC/custom IC design flow.
• Excellent debugging skills for RTL, analog blocks and gate-level simulations.
• Experience with DFT tools (e.g. TetraMAX, Modus or Tessent), ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
• Experience in developing test benches and simulation in RTL/GATE/SDF environments.
• Familiarity with scripting languages such as Python, Perl, or TCL for automation.
• Solid understanding of semiconductor manufacturing processes and fault models.
• Knowledge of FPGA architecture/design flow, various BIST is a strong plus.
• Strong analytical and problem-solving skills to diagnose complex issues.
• Good communication skills and the ability to work with cross functional teams.
Apply on the employer's site
Original posting: efinixinc.com
RISC-V ecosystem
Efinix Inc in the RISC-V ecosystem
RISC-V International: Strategic
Our mission is to drive the future of edge computing w/our Trion® FPGA silicon platform.
- FPGA vendor promoting RISC-V SoCs on its devices ("RISC-V SoCs: Powering Embedded Computing")
- RISC-V soft cores used across its Trion/Titanium FPGA product lines
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