Logic Designer (2025)

ASIC RTL Designer (Job title and responsibilities commensurate with experience) Atmosic Technologies is looking for a low-power, high-performance RTL designer who is passionate about delivering innovative low-power and battery-free wireless connectivity solutions. Responsibilities: • Design and develop low-power SoC (system-on-a-chip) for wireless connectivity Implement digital circuits and systems to push the limit of low-power solutions based on high-level specification Implement low-power design techniques to meet application requirements while maintaining performance Map ASIC RTL to FPGA while minimizing code base differences Define and bring up FPGA platforms for pre-silicon validation and software development Create and execute test plans for validating SoC functionality and performance Debug and resolve system level issues that may span multiple disciplines Requirements: • Minimum of 2 years of relevant industrial design experience, exceptional new graduates will be considered Scripting or programming experience in Python or C/C++ Knowledge of low-power design methodologies Ability to write and analyze the completeness of constraints Familiarity with lab equipment including logic analyzers, oscilloscopes, and multimeters Strong analytical and debugging skills BS in Electrical Engineering or equivalent required, MS preferred Nice to Have: • Familiarity with ARM or RISC-V architectures, Xilinx FPGAs, and Vivado tool chain Experience with validating and debugging low-power wireless systems Understanding of common interfaces and bus protocols (e.g. I2C, SPI, AHB) Knowledge of wireless protocols (e.g. Bluetooth Low Energy) Location: • Hiring in multiple geographies: Campbell (Silicon Valley), California or Hsinchu, Taiwan Salary range • $125,000 to $180,000 (Campbell) •