Senior/Principal Analog Mixed-Signal Design Engineer, Optical Receiver

**Job Title** Senior/Principal Analog Mixed-Signal Design Engineer, Optical Receiver **About the Role** Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We are looking for analog mixed-signal engineers to design the receiver front-end that turns photodetector current into clean digital data across many parallel lanes. You will own circuits from specification through post-layout signoff and silicon correlation, working closely with the RX lead, layout and the digital team. We are hiring at senior through principal level; title and scope will match experience. **Key Responsibilities** - Design and simulate receiver circuits: photodetector interface, transimpedance amplifiers, limiting and post-amplifiers, equalization, comparators and slicers, offset cancellation and signal detection. - Analyze noise, bandwidth, sensitivity, crosstalk and power per lane across PVT corners and Monte Carlo. - Design calibration and trim circuits, and define their control interface with the digital team. - Work with layout on floorplans, matching and parasitic-sensitive routing for dense receiver arrays; run post-layout extraction and verification. - Deliver behavioral models (Verilog-A or real-number models) and correlate them with transistor-level results. - Write block specifications and present at design reviews. - Support silicon bring-up and correlate measurements with simulation. **At the principal level, you will also** - Set the technical direction for receiver circuits and front-end architecture trade-offs with the RX lead and system architect. - Lead design reviews and define verification and signoff criteria for RX blocks. - Mentor engineers and review their designs. **Qualifications** **Required** - MS or PhD in Electrical Engineering (or BS with equivalent experience) and 5+ years of analog/mixed-signal design. - Taped-out high-speed receiver circuits such as TIAs, CTLEs, limiting amplifiers or comparators for optical or wireline links. - Design experience in FinFET or other advanced CMOS processes. - Proficiency with Cadence Virtuoso and Spectre, including noise, AC, transient and Monte Carlo analysis. - Experience taking blocks through post-layout extraction and signoff. **Preferred** - Optical receivers or photodiode interfaces. - Multi-Gb/s wireline receivers or arrays of parallel lanes. - Behavioral modeling in Verilog-A or SystemVerilog real-number models. - Hands-on lab characterization. - MATLAB or Python for analysis and automation. - 10+ years with technical leadership of receiver designs through production (principal level). **Key Competencies** - Analytical: reasons from first principles about noise, bandwidth and power. - Ownership: carries a block from specification to silicon. - Collaboration: works closely with layout, digital and system architecture. - Clear communicator: documents designs and trade-offs concisely.