Design Verification Engineer
RTL / HDLVerificationFPGAPosted Oct 20, 2026
Overview
- Added in 30 days
- 32
- At this company, still open
Skills named in this posting
- SystemVerilog
- Verilog
- VHDL
- UVM
- PCIe
- Ethernet
- Python
- Tcl
Design Verification Engineer
Location: Penang, Malaysia
Responsibilities:
• Create verification and validation plan based on IP/FPGA architecture specifications and carry out all the validation tasks. The plan should include functional, system level and fullchip verification and validation perspectives.
• Developing IP/subsystem/system level/fullchip testbench, create tests, and necessary coverage goals based on specification to verify the design.
• Carry out the results review against the coverage goals. Track and improve the tests to ensure the desire coverage is met.
• Support cross-functional teams in IP functional validation tests for IP bring-up on actual FPGA.
• Standardizing verification and validation framework, drive system test design implementation and overall IP system validation on HW.
• Define and develop verification and validation tools and flows to reduce the verification time.
• Interfacing with 3rd party vendors for latest industry tool and methodology evaluation.
• Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time-to-market.
Qualifications:
• Bachelor’s or Master’s Degree in Engineering in Electrical / Electronics or equivalent.
• More than 5 years of working experience in IC design verification.
• Experienced in creating and executing validation plans Is preferred.
• Experienced in creating testbenches for design verification/validation according to test plans.
• Experienced in mentor or leading a verification or validation team is a plus.
• Knowledge with verification tools and methodologies.
• Familiar in RTL design with Verilog and/or VHDL is a strong pl.
• Familiar with advanced verification methodologies such as UVM, OVM, VMM, System Verilog, constrained-random verification, assertion-based verification, and functional coverage techniques is a strong plus.
• Knowledge of IP protocol, e.g., memory interface protocol (DDR, HBM, etc.) or high speed interfaces (PCIe, Ethernet, etc.) is a strong plus.
• Familiar with Perl, Tcl, Python, and shell scripts is a plus.
• Good debugging, problem solving and analytical skills.
Apply on the employer's site
Original posting: efinixinc.com
RISC-V ecosystem
Efinix Inc in the RISC-V ecosystem
RISC-V International: Strategic
Our mission is to drive the future of edge computing w/our Trion® FPGA silicon platform.
- FPGA vendor promoting RISC-V SoCs on its devices ("RISC-V SoCs: Powering Embedded Computing")
- RISC-V soft cores used across its Trion/Titanium FPGA product lines
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