Package Integration and SI/PI Engineer

**Job Title** Package Integration and SI/PI Engineer **About the Role** Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We are looking for a package integration and SI/PI engineer to own the boundary between our ASIC and its package. You will make sure high-speed signals, clocks and power reach the chip cleanly, and that package constraints are reflected in the chip design early. **Key Responsibilities** - Own the die-package boundary for the ASIC: bump and pad map inputs, and signal and power assignment with the package team. - Perform signal integrity analysis of high-speed and clock paths across die, package and board: channel extraction, crosstalk and return paths. - Perform power integrity analysis from die through package to board: impedance targets, supply noise and ripple, and on-die and package decoupling. - Build and exchange chip power and package models, and run die-package co-simulation with the chip team. - Provide power maps for thermal analysis. - Define ESD and supply strategy with the core analog and layout teams. - Run die/package feasibility reviews and correlate models with lab measurements. **Qualifications** **Required** - MS in Electrical Engineering (or BS with equivalent experience) and 5+ years of SI/PI work on high-speed ICs and packages. - Experience with tools such as Ansys HFSS, SIwave and RedHawk, Cadence Sigrity and Clarity, or Keysight ADS. - Strong grasp of S-parameters, TDR, transmission lines and PDN design. - Flip-chip package integration experience. **Preferred** - 2.5D/3D or other advanced packaging. - Optical or co-packaged optics modules. - Lab measurement with VNA and oscilloscopes. - Python or MATLAB automation. **Key Competencies** - Systems view: thinks across die, package and board. - Analytical: grounds decisions in models and measurements. - Collaboration: bridges chip and package teams. - Clear communicator: turns analysis into concrete constraints.