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Physical Design Engineer

Efinix Inc

Physical designPosted Oct 20, 2026
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Skills named in this posting

  • Tcl
  • Perl
Physical Design Engineer Location: Penang, Malaysia Responsibilities: • Implement all physical design related aspects from power distribution planning; Placement and optimization (timing/area/power); Clock network planning; Clock tree synthesis/balancing; layout timing optimization and Signal/Power Integrity analysis, Power Analysis. • Perform all necessary physical verification for the layout designed to ensure the layout meets its desired functionality and all manufacturing requirements. • Propose and/or implement enhancement for tools, flows and methodologies to improve layout design efficiency. • Communicate regularly with the project lead and potentially project teams worldwide to resolve issues and to ensure meeting targeted goals and schedule. Requirements: • Bachelor’s or Master’s in Engineering in Electrical / Electronics or equivalent. • 1-20 years of working experience in physical design field. • Understand the IC layout aspect, e.g., floor-planning, timing. • Knowledge with layout design tools and methodologies. • Knowledge in physical design: floor planning, placement and area optimization, clock network planning, power distribution planning and routing. • Post layout physical verification and DFM rules (Mentor Calibre/Cadence PVS). • Scripting skills in SKILL, Perl, Tcl and Shell, with good understanding of UNIX/LINUX.

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Original posting: efinixinc.com

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RISC-V ecosystem

Efinix Inc in the RISC-V ecosystem

RISC-V International: Strategic

Our mission is to drive the future of edge computing w/our Trion® FPGA silicon platform.

  • FPGA vendor promoting RISC-V SoCs on its devices ("RISC-V SoCs: Powering Embedded Computing")
  • RISC-V soft cores used across its Trion/Titanium FPGA product lines

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