Senior Staff ASIC Design Engineer – 4G/5G/6G Modem

About EdgeQ EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices. Experience: 10+ Years Location: Santa Clara, US Responsibilities • Define the overall HW architecture of major 4G/5G modem blocks for gNB and UE, terrestrial and NTN • Translate 3GPP, system, and algorithm requirements into architecture and micro-architecture specifications with clear PPA targets • Drive HW/SW partitioning between fixed-function HW accelerators, vector processing engines, and CPUs/firmware • Perform architecture exploration and modeling (throughput, latency, memory bandwidth, timeline budgets) to size compute and memory resources • Architect power and area efficient datapaths, memory subsystems, and control for channel estimation, MIMO equalization, channel coding/decoding, and NTN compensation • Lead block-level and subsystem-level RTL design teams; review micro-architecture, RTL, and verification plans • Own PPA closure of major blocks together with physical design, ensuring timing, area, and power goals are met • Collaborate with algorithm, firmware/software, verification, DFT, and physical design teams throughout the chip development cycle • Support post-silicon bring-up, debug, and performance characterization • Mentor staff and junior engineers and set design methodology and quality standards Job Requirements • BS/MS/PhD in Electrical/Computer Engineering or related field with 10+ years of ASIC design experience • Proven track record of architecting and taping out major baseband blocks or subsystems in high-volume wireless SoCs • Hands-on architecture experience with key PHY blocks such as FFT/IFFT, channel estimation, MIMO detection (MMSE/ML), beamforming, LDPC/Polar/Turbo codecs, rate matching, HARQ, and digital front-end • Experience with vector/DSP processors or RISC-V-based programmable engines and HW/SW partitioning of PHY processing • Experience with both gNB (base station) or UE (device) baseband requirements, including multi-cell/multi-user scaling, throughput, and latency budgets • Experience with multiple clock domains, asynchronous interfaces, on-chip interconnects (AXI/NoC), and SRAM/DDR memory subsystems • Expert in power, performance and area (PPA) trade-offs: fixed-point analysis, memory partitioning/banking, clock and power gating, DVFS, and low-power design (UPF) • Expert in SystemVerilog RTL and front-end flows (Lint, CDC/RDC, LEC, synthesis, STA constraints, power analysis) • Deep knowledge of digital signal processing and wireless communication; expert understanding of 4G LTE / 5G NR physical layer (3GPP Rel-15 onward) • Knowledge of 5G NTN (satellite) requirements such as large Doppler/timing pre-compensation, long round-trip delay, and HARQ/timing-advance handling is a strong plus • Excellent written and verbal communication; able to lead cross-functional technical discussions and mentor engineers Apply Now