Staff Digital Design Engineer GPU Hardware - Athens
Qualcomm Technologies, Inc.
Marousi, GreeceRTL / HDLVerificationPhysical designSoC / ASIC2026-10-20
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505 results · page 3 of 21 · dates: UTC
ASIC Backend Engineer
RaiderChip
On-Site (Solares, Spain) • Full-timeRequirements: • Own the technical oversight of ASIC back-end executed by design service partners • Review, challenge, and validate P&R, timing closure, DRC/LVS, and sign-off results • Define and review backend constraints and deliverables • Strong understanding of physical design flows and trade-offs • Working experience with Synopsys tools • Proven experience with full ASIC tapeouts (strong plus)SoC / ASIC2026-10-20ASIC Verification Engineer
RaiderChip
On-Site (Solares, Spain) • Full-timeRequirements: • Develop and execute comprehensive verification strategies for ASIC designs • Create simulation environments to aggressively validate functionality • Leverage existing FPGA-proven designs as reference and validation baseline • Strong experience with RTL simulation and verification methodologies • Working experience with Synopsys toolsVerificationSoC / ASIC2026-10-20FPGA Engineer (Prototyping)
RaiderChip
On-Site (Solares, Spain) • Full-timeRequirements: • Use FPGA emulation to stress, debug, and validate ASIC-designs • Leverage long-running, proven FPGA prototypes as functional reference • Validate functionality through SW simulation and HW emulation • Collaborate closely with ASIC frontend and verification engineers • Drive issue detection, root-cause analysis, and fix validation • Strong experience with RTL simulation and FPGA toolchains (AMD/Xilinx)FPGA2026-10-20ASIC Digital Physical Design Engineer
Nordic Semiconductor ASA
Bristol, Stockholm, TamperePhysical designSoC / ASIC2026-10-20ASIC RTL Design Engineer
Nordic Semiconductor ASA
Bristol, StockholmRTL / HDLVerificationCompilersPhysical design2026-10-20- Hsinchu, Hsinchu County, TaiwanRISC-VRTL / HDLVerificationFirmware2026-10-20
Design Engineers & Engineering Leads
Netrasemi
Area: ASIC Design & Verification/ Embedded system / AI/ML Software/ Physical Design & Verification2026-10-20- Santa Clara, USRTL / HDLVerificationPhysical designSoC / ASIC2026-10-20
- Santa Clara, USRISC-VRTL / HDLCompilersFirmware2026-10-20
- Santa Clara, USRISC-VRTL / HDLCompilersSoC / ASIC2026-10-20
- Santa Clara, USRTL / HDLVerificationPhysical designSoC / ASIC2026-10-20
- Santa Clara, USRISC-VRTL / HDLFirmwarePhysical design2026-10-20
- Santa Clara, USRISC-VRTL / HDLCompilersSoC / ASIC2026-10-20
ASICS Design Engineer, Senior Staff to Principal Level
Qualcomm Technologies, Inc.
Hsinchu City, Taiwan, Taipei, Taipei City, TaiwanRTL / HDLPhysical designSoC / ASIC2026-10-19Senior DTCO Engineer, CPU Physical Design
NVIDIA Corporation
US, CA, Santa Clara, US, TX, Austin, US, OR, HillsboroPhysical design2026-10-19Senior Mixed Signal Circuit Design Engineer
NVIDIA Corporation
Taiwan, Hsinchu, Taiwan, TaipeiPhysical design2026-10-19Senior Board Design Hardware Engineer
NVIDIA Corporation
Taiwan, TaipeiFirmwareFPGA2026-10-19Senior Circuit Design Engineer
NVIDIA Corporation
US, CA, Santa ClaraRTL / HDLPhysical designSecurity2026-10-19Physical Design Engineer
Qualcomm Technologies, Inc.
San Diego, California, United States of AmericaRTL / HDLVerificationCompilersPhysical design2026-10-19ASICS Design Verification Engineer-Senior
Qualcomm Technologies, Inc.
San Diego, California, United States of AmericaRTL / HDLVerificationSoC / ASIC2026-10-19- Yerevan, ArmeniaRTL / HDLVerificationPhysical designSoC / ASIC2026-10-19
EVA Design Verification Engineer, Senior - Cork, Ireland
Qualcomm Technologies, Inc.
Cork, IrelandRTL / HDLVerificationFirmwareSoC / ASIC2026-10-16- Markham, CanadaRTL / HDLVerificationPhysical designSoC / ASIC2026-10-16
- Hyderabad, IndiaRTL / HDLPhysical designSoC / ASIC2026-10-16
