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926 results · page 5 of 38 · dates: UTC
On-Site (Solares, Spain) • Full-timeRequirements:
• Own the technical oversight of ASIC back-end executed by design service partners
• Review, challenge, and validate P&R, timing closure, DRC/LVS, and sign-off results
• Define and review backend constraints and deliverables
• Strong understanding of physical design flows and trade-offs
• Working experience with Synopsys tools
• Proven experience with full ASIC tapeouts (strong plus) SoC / ASIC 2026-10-20
On-Site (Solares, Spain) • Full-timeRequirements:
• Develop and execute comprehensive verification strategies for ASIC designs
• Create simulation environments to aggressively validate functionality
• Leverage existing FPGA-proven designs as reference and validation baseline
• Strong experience with RTL simulation and verification methodologies
• Working experience with Synopsys tools Verification SoC / ASIC 2026-10-20
On-Site (Solares, Spain) • Full-timeRequirements:
• Use FPGA emulation to stress, debug, and validate ASIC-designs
• Leverage long-running, proven FPGA prototypes as functional reference
• Validate functionality through SW simulation and HW emulation
• Collaborate closely with ASIC frontend and verification engineers
• Drive issue detection, root-cause analysis, and fix validation
• Strong experience with RTL simulation and FPGA toolchains (AMD/Xilinx) FPGA 2026-10-20
Hsinchu, Hsinchu County, Taiwan RISC-V RTL / HDL Verification Firmware 2026-10-20
RTL / HDL Physical design SoC / ASIC FPGA 2026-10-20
2026-10-20
RTL / HDL Verification Compilers SoC / ASIC 2026-10-20
RTL / HDL Verification Compilers SoC / ASIC 2026-10-20
RTL / HDL SoC / ASIC 2026-10-20
Paris,
France RTL / HDL Verification SoC / ASIC 2026-10-20
Biot,
France RTL / HDL Verification SoC / ASIC 2026-10-20
Biot,
France RTL / HDL Verification SoC / ASIC Security 2026-10-20
Santa Clara, California, United States of America, Austin, Texas, United States of America, Essex Junction, Vermont, United States of America, Malta, New York, United States of America 2026-10-20
Palo Alto Office RTL / HDL Physical design SoC / ASIC 2026-10-19
Palo Alto Office RTL / HDL Verification Physical design SoC / ASIC 2026-10-19
Palo Alto Office Compilers Physical design 2026-10-19
Palo Alto Office RTL / HDL Verification Physical design 2026-10-19
Austin, TX 2026-10-19
Cadence Design Systems, Inc.
SAN JOSE SoC / ASIC 2026-10-19
Cadence Design Systems, Inc.
SAN JOSE 2026-10-19
Qualcomm Technologies, Inc.
Hsinchu City, Taiwan, Taipei, Taipei City, Taiwan RTL / HDL Physical design SoC / ASIC 2026-10-19
Taiwan, Hsinchu, Taiwan, Taipei Physical design 2026-10-19
Taiwan, Taipei Firmware FPGA 2026-10-19
Qualcomm Technologies, Inc.
Markham, Ontario, Canada Physical design SoC / ASIC 2026-10-19
US-AZ-TUCSON-9070 ~ 9070 S Rita Rd ~ BLDG 9070 2026-10-17
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