Principal PCIe CXL RTL Design Engineer
Rambus Inc.
FR-Aix-en-Provence | BG-SOFIA | US-OR-Hillsboro | IN-KA-BangaloreRTL / HDL2026-08-11
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3,179 results · page 92 of 128 · dates: UTC
Hardware Design Engineer
Rambus Inc.
US-OR-Hillsboro2026-08-11Circuit Design Engineer
proteanTecs
Israel - Haifa2026-08-11Senior Logic Design Engineer
proteanTecs
Israel - HaifaRTL / HDLVerificationPhysical designSoC / ASIC2026-08-11- USA - Santa Clara, CARTL / HDLVerificationSoC / ASIC2026-08-11
- Austin, TexasRTL / HDLVerificationSoC / ASIC2026-08-11
- Boxborough, MassachusettsRTL / HDLVerification2026-08-11
Senior Design Engineer-CPU
NextSilicon
IsraelRISC-VSoC / ASICFPGA2026-08-11Senior Logic Design Engineer
NextSilicon
IsraelRTL / HDL2026-08-11Masterarbeit: Design of Experiments Power Engines
Fraunhofer Gesellschaft
Paderborn2026-08-11GPU Hardware Datapath Design Engineer
Imagination Technologies Group Ltd.
Kings Langley UKRTL / HDLVerificationPhysical designSoC / ASIC2026-08-11Senior GPU Hardware Design Engineer
Imagination Technologies Group Ltd.
Kings Langley UK, Bristol UKRTL / HDLVerificationPhysical designSoC / ASIC2026-08-11Staff GPU Hardware Design Engineer
Imagination Technologies Group Ltd.
Kings Langley UK, Bristol UKRTL / HDLVerificationPhysical designSoC / ASIC2026-08-11Senior Analog and Mixed Signal Integrated Circuit Design Research Engineer
Fondazione Chips-IT
2026-08-11Design Verification Engineer SoC
Fondazione Chips-IT
RTL / HDLVerificationSoC / ASIC2026-08-11Junior Digital Design and RISC-V Architectures Engineer
Fondazione Chips-IT
RISC-VRTL / HDLFirmwareSoC / ASIC2026-08-11Principal Physical Digital Design Engineer
Fondazione Chips-IT
RTL / HDLPhysical designSoC / ASIC2026-08-11- Zurich, CHRemoteRTL / HDL2026-08-11
- Poznan, Wroclaw, Gdansk, Katowice, GothenburgRISC-VRTL / HDLVerificationSoC / ASIC2026-08-11
Digital design/FPGA Engineer
Antmicro
Poznan, Wroclaw, Gdansk, Katowice, GothenburgRTL / HDLVerificationCompilersFirmware2026-08-11- Poznan, Wroclaw, Gdansk, GothenburgRTL / HDLCompilersPhysical designSoC / ASIC2026-08-11
- Portland, OR, US; Austin, TX, USPhysical design2026-08-11
Senior CPU Microarchitecture & Logic Design Engineer
Ahead Computing
Guadalajara, MXRTL / HDLPhysical design2026-08-11CPU Microarchitecture & Logic Design Engineer
Ahead Computing
Guadalajara, MXRTL / HDLPhysical design2026-08-11Senior Physical Design Engineer – CPU PPA Optimization
Ahead Computing
Guadalajara, MXRTL / HDLPhysical design2026-08-11
