Tel AvivRTL / HDLFirmwareSoC / ASICFPGA2026-10-27
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159 results · page 1 of 7 · dates: UTC
- US-IA-CEDAR RAPIDS-193 ~ 1120 Collins Rd NE ~ BLDG193RTL / HDLSoC / ASICFPGA2026-10-27
Lead FPGA Timing & Characterization Silicon Design Engineer
Advanced Micro Devices (AMD)
Hyderabad, IndiaPhysical designFPGA2026-10-27Staff Design Verification Engineer – SoC and eFPGA
Analog Devices, Inc.
US, TX, Austin, Plaza on the LakeRTL / HDLVerificationFirmwareSoC / ASIC2026-10-27Solution Architect, FPGA/SoC - AECG
Advanced Micro Devices (AMD)
San Jose, CaliforniaFirmwareSoC / ASICFPGA2026-10-26- US-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDGRTL / HDLFirmwarePhysical designFPGA2026-10-26
- US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150ARTL / HDLVerificationPhysical designSoC / ASIC2026-10-26
- US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150ARTL / HDLVerificationPhysical designSoC / ASIC2026-10-26
- Research & development - LeuvenRTL / HDLCompilersFirmwarePhysical design2026-10-26
- US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150ARTL / HDLVerificationFirmwarePhysical design2026-10-23
- Sunnyvale, CaliforniaRTL / HDLVerificationSoC / ASICFPGA2026-10-23
- US-TX-MCKINNEY-513WC ~ 2501 W University Dr ~ WING C BLDGRTL / HDLVerificationFirmwarePhysical design2026-10-22
Senior FPGA Engineer
Synopsys
Moreira, PortugalRTL / HDLVerificationCompilersPhysical design2026-10-22Senior FPGA Prototyping Engineer - Hardware
NVIDIA Corporation
US, CA, Santa ClaraRTL / HDLVerificationPhysical designSoC / ASIC2026-10-20ASIC Verification Engineer
RaiderChip
On-Site (Solares, Spain) • Full-timeRequirements: • Develop and execute comprehensive verification strategies for ASIC designs • Create simulation environments to aggressively validate functionality • Leverage existing FPGA-proven designs as reference and validation baseline • Strong experience with RTL simulation and verification methodologies • Working experience with Synopsys toolsVerificationSoC / ASIC2026-10-20FPGA Engineer (Prototyping)
RaiderChip
On-Site (Solares, Spain) • Full-timeRequirements: • Use FPGA emulation to stress, debug, and validate ASIC-designs • Leverage long-running, proven FPGA prototypes as functional reference • Validate functionality through SW simulation and HW emulation • Collaborate closely with ASIC frontend and verification engineers • Drive issue detection, root-cause analysis, and fix validation • Strong experience with RTL simulation and FPGA toolchains (AMD/Xilinx)FPGA2026-10-20- RTL / HDLVerificationCompilersPhysical design2026-10-20
- FPGA2026-10-20
System Solutions FPGA Engineer
Efinix Inc
RISC-VRTL / HDLVerificationKernel / Linux2026-10-20Senior FPGA Engineer H/F
Arteris IP
Biot, FranceRTL / HDLVerificationCompilersSoC / ASIC2026-10-20- Palo Alto OfficeRTL / HDLFirmwarePhysical designSoC / ASIC2026-10-19
FPGA Systems Development Engineer
Analog Devices, Inc.
Denmark, CopenhagenRTL / HDLVerificationFirmwareSoC / ASIC2026-10-17- US-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDGRTL / HDLVerificationFirmwarePhysical design2026-10-16
- US-AZ-TUCSON-M02 ~ 1151 E Hermans Rd ~ BLDG M02RTL / HDLVerificationFirmwarePhysical design2026-10-16
- US-CA-FULLERTON-675 ~ 1801 Hughes Dr ~ BLDG 675RTL / HDLVerificationFPGA2026-10-15
