关于我们:RiVAI technology ltd (睿思芯科) RiVAI technology ltd (睿思芯科) 位于深圳,子公司成都/香港。专注于为数据中心市场开发下一代高性能 RISC-V 微处理器。 • 创新前沿: 我们的创始人是 RISC-V 创始团队成员。我们拥有大量国际顶尖院校背景的工程师,致力于采用非传统设计方法突破处理器性能极限。 主要职责 - 参与芯片后端设计各方面工作,包括FloorPlan,、电源分配、时序优化、布局布线等 - 完成Docu
Physical design jobs 2,038
Physical design, place-and-route, timing closure and backend flows.
Roles 1,861–1,890 of 2,038, newest first.
- 深圳RISC-VPhysical designApr 1, 2026
Senior Logic Design Engineer, CPU Core
NVIDIA Corporation
Israel, YokneamRTL / HDLPhysical designApr 1, 2026The NVIDIA CPU team is a world-class, global organization united by a mission to push the boundaries of what’s possible and shape the future of computing. We are looking for a talented, fast-learning and highly motivated Senior Logic Design
CPU/GPU R2G Engineer
MediaTek Inc
HsinChuRTL / HDLPhysical designMar 31, 2026Responsible for RTL to GDS design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS. Involve in activities encompass physical design and analysis of complex and timi
SoC Integration IC Design Engineer
MediaTek Inc
HsinChuPhysical designSoC / ASICMar 29, 20261. Flagship Smartphone chip integration 2. Automotive SoC chip integration 3. Chip integration methodology and automation tool development 4. Timing constraint and analysis 5. SoC Floorplan Architecture 6. SoC Clock Architecture #LI-LL1
Memory Controller Digital Engineer
MediaTek Inc
HsinChuRTL / HDLPhysical designMar 29, 20261. Memory system architecture design and RTL implementation on SOC 2. DRAM controller IP development, include high-speed digital PHY, high-efficiency scheduler, low power management unit, and design for test. 3. DRAM controller IP integrati
SoC Architecture and Integration Engineer
MediaTek Inc
HsinChuRTL / HDLPhysical designSoC / ASICMar 29, 20261. Clock architecture and RTL design 2. SOC IOMUX architecture and RTL Design 3. SoC Floorplan Architecture 4. Flagship Smartphone chip integration 5. Automotive SoC chip integration #LI-LL1
HSI SW / System development engineer
MediaTek Inc
HsinChuPhysical designMar 29, 20261. HSI (USB, PCIE, MIPI, UFS, DP, HDMI,...) system SW (Driver/FW) - design and validation 2. HSI (USB, PCIE, MIPI, UFS, DP, HDMI,...) system HW (PCB/PHY) - design, validation, and PPA analyzing #LI-LL1
Staff Silicon Engineer
Cognichip
🇺🇸 Redwood CityRTL / HDLVerificationPhysical designMar 26, 2026**Job Title** Staff Silicon Engineer **About Cognichip** - At Cognichip, we are building AI-native tools that transform how semiconductor engineers create, verify, and optimize chips. - Our platform combines large proprietary models, age
Technical Program Manager, Architecture
Tenstorrent
Santa Clara, California, United StatesRISC-VRTL / HDLVerificationMar 23, 2026Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software
Power Analysis and Optimization Engineer
NVIDIA Corporation
China, ShanghaiRTL / HDLVerificationPhysical designMar 23, 2026Not only pursuing the outstanding chip performance, NVIDIA also keeps chasing for the power efficiency in every product. Perf-per-Watt is crucial to us. Power Analysis and Optimization Team is responsible for helping IP teams to define powe
High‑Speed IP Integration Engineer, Up to Snr Staff (USB/PCIe/UHS) (Hsinchu, Taipei)
Qualcomm Technologies, Inc.
Hsinchu City, Taiwan, Taipei, Taipei City, TaiwanRTL / HDLVerificationCompilersMar 20, 2026Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a forward-thinking technology company, Qualcomm advances the limits of innovation in "Industrial and Embedded
Senior Silicon Engineer
Cognichip
🇺🇸 Redwood CityRTL / HDLVerificationPhysical designMar 18, 2026**Job Title** Senior Silicon Engineer **Job description** **About the Job** At Cognichip, we are building the next-generation enterprise product suite to empower semiconductor design engineers to achieve a 10x productivity boost using p
Senior Logic Design Engineer, Cache Coherent Interconnects
NVIDIA Corporation
US, CA, Santa Clara, US, OR, HillsboroRTL / HDLPhysical designSoC / ASICMar 18, 2026We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusi
Senior Mask Design Engineer - Hardware
NVIDIA Corporation
US, CA, Santa ClaraPhysical designSoC / ASICMar 17, 2026NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep lear
CPU RTL Design Engineer
Qualcomm Technologies, Inc.
Hsinchu City, TaiwanRISC-VRTL / HDLPhysical designMar 17, 2026Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Position corresponds to development of ARM/RISC-V architecture based complex CPU subsystem. Engineer will work in
Senior CPU Design Engineer
NVIDIA Corporation
US, OR, Hillsboro, US, TX, Austin, US, MA, Westford, Remote - US, US, CA, Remote, US, CA, Santa ClaraRemoteRTL / HDLVerificationPhysical designMar 16, 2026We are looking for a Senior CPU Design Engineer! NVIDIA is seeking best-in-class CPU Design Engineers to design the world’s leading CPUs. This position offers you the opportunity to have a real impact in a dynamic, technology-focused compan
ASIC Engineer
Falcomm
Atlanta, Georgia, United StatesRTL / HDLVerificationPhysical designMar 12, 2026Are you passionate about building advanced semiconductor systems that power next-generation wireless technologies? At Falcomm, we are transforming innovative semiconductor research into real-world products through energy-efficient RF power
- Atlanta, Georgia, United StatesVerificationPhysical designMar 12, 2026
Are you passionate about designing advanced semiconductor layouts that enable next-generation wireless technologies? At Falcomm, we are transforming innovative semiconductor research into real-world solutions through high-performance, energ
Processor Architect
Fractile
LondonRTL / HDLCompilersPhysical designMar 11, 2026About Fractile Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the
Processor Architect
Fractile
BristolRTL / HDLCompilersPhysical designMar 11, 2026About Fractile Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the
NPU/AI Processor Architecture (RTL) design- Staff/Sr Staff
Qualcomm Technologies, Inc.
Bangalore, IndiaRISC-VRTL / HDLPhysical designMar 11, 2026Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm's Hexagon NPU Team is hiring for the various positions in Bangalore (India) location for the developm
- BangaloreRTL / HDLCompilersPhysical designMar 10, 2026
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and densi
- HsinChuRTL / HDLPhysical designMar 10, 2026
1. High Speed digital design implementation 2. Integration from RTL to gate level, including flow QC, timing closure and issue analysis & solving 3. Signoff on design with mixed-signal interface 4. Design methodology and integration flow im
CPU Post-Silicon Validation Engineer - Multiple Levels
Qualcomm Technologies, Inc.
Santa Clara, California, United States of America, Austin, Texas, United States of America, San Diego, California, United States of AmericaVerificationCompilersFirmwareMar 6, 2026Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a “CPU Silicon Bring up and Validation Engineer” you would be part of the CPU Silicon Bringup Team, within the CPU
Experienced Physical Design Engineer
Mobileye Vision Technologies Ltd.
Haifa, IsraelRTL / HDLPhysical designSoC / ASICMar 4, 2026Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to
Experienced Physical Design Engineer
Mobileye Vision Technologies Ltd.
Petah Tikva, IsraelRTL / HDLPhysical designSoC / ASICMar 4, 2026Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to
2026 Intern-Physical Design Engineer
Qualcomm Technologies, Inc.
Shanghai, ChinaRTL / HDLPhysical designMar 4, 2026Company: Qualcomm China Job Area: Interns Group, Interns Group > Interim Engineering Intern - SW General Summary: 1. Handle synthesis/DFT logic insertion and ATPG pattern generation. 2. Handle physical design tasks from verilog netlist
2026 Intern-Digital Design/Verification Engineer
Qualcomm Technologies, Inc.
Shanghai, ChinaRTL / HDLVerificationPhysical designMar 4, 2026Company: Qualcomm China Job Area: Interns Group, Interns Group > Interim Engineering Intern - SW General Summary: 1. ASIC IP/SoC design and verification 2. Participate in whole ASIC flow, including development of micro architecture spec
CPU STA - Sr/Lead/Staff/Sr Staff Engineer
Qualcomm Technologies, Inc.
Hyderabad, Telangāna, IndiaRTL / HDLVerificationPhysical designMar 4, 2026Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineer
SOC Architect - Chiplet
Tenstorrent
Munich, GermanyRISC-VCompilersPhysical designMar 2, 2026Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software