Graduate Formal Verification Engineer

Job overview Our Graduate Program is designed for recent UK-based graduates ready to start in 2026. During the program, you’ll go through training & work on real projects to tackle challenges that push you to think fast and adapt. Your job would involve building cutting-edge formal verification testbench environments to find bugs and build proofs of bug absence in SoCs containing processors, video/GPUs, networking, AI/ML designs. Responsibilities: • Develop formal verification environments and write assertions to validate RTL designs against specifications. • Perform formal analysis to identify bugs, corner cases, and unintended behaviours. • Debug counterexamples and collaborate with design/verification teams to resolve issues. • Support equivalence checking and contribute to verification planning and coverage closure. • Improve verification flows, automation, and documentation while staying current with formal methodologies. Requirements: Education Bachelor/Masters/Doctorate in EEE/ECE/CS/Maths/Physics Technical Skills: Linux/Unix Verilog/ SystemVerilog/VHDL Digital design Language skills English “Nice To Have” Skills and Experience: Exposure to open-source projects in design/verification RISC-V/Arm/x86/MIPS SVA/PSL/Theorem proving Tcl/Python/Bash Git version control Soft Skills Problem solving Ownership Autonomy Team spirit Attention to detail Right to work We welcome graduates on a graduate visa, that upon successful completion of their probation/graduate program period will be sponsored for Skilled Worker Visa. In Return: You’ll apply your formal verification expertise to technologies that shape and support millions of devices for years to come. This role gives you the opportunity to step into a field where you can grow your technical leadership and impact.