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Analog/Mixed-Signal (PMIC) IC Design Lead

Celera

RTL / HDLPosted Oct 20, 2026
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Skills named in this posting

  • SystemVerilog
  • Verilog
  • Mixed-signal
Summary As the Design Lead, you will spearhead the design and development of high-performance PMIC products. You will lead a multidisciplinary team to define chip architectures, oversee mixed-signal implementation, and ensure successful tape-outs that meet aggressive performance and schedule targets. Key Responsibilities • Technical Leadership: Direct and participate in the full IC development lifecycle, including research, design, and evaluation of PMIC products. • Architecture &Specification: Define system-level architectures and write detailed specifications for analog and mixed-signal blocks such as LDOs, Buck/Boost converters, and Battery Management systems. • Design & Verification: Lead full-chip integration and top-level simulations; drive verification strategies to ensure design completeness across all process corners. • Cross-Functional Collaboration: Partner with Digital Design, Verification, Layout, and Test Engineering teams to resolve complex trade-offs between power, area, and performance. • Silicon Debug & Characterization: Lead post-silicon validation, bench correlation, and root-cause analysis during debug phases to ensure production readiness. Required Qualifications • Education: Bachelor’s, Master’s, or PhD in Electrical Engineering with a focus on power electronics or microelectronics. • Experience: 10+ years of relevant IC design experience, with a proven track record of releasing multiple PMIC products into high-volume manufacturing. • Technical Expertise: Expertise in analog/mixed-signal blocks: Bandgaps, OP-Amps, high-efficiency switching regulators, and data converters (ADC/DAC). Proficiency with industry-standard EDA tools (Cadence Virtuoso, Spectre) and modeling languages (Verilog-AMS, SystemVerilog). • Process Knowledge: Good understanding of BCD process technologies Strong grasp of semiconductor device physics and design for EMI/EMC and ESD protection. Preferred Skills • Familiarity with digital control architectures and industry-standard protocols Location: Prefer Santa Clara, CA.

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Original posting: celerasemi.com

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RISC-V ecosystem

Celera in the RISC-V ecosystem

Automated analog/mixed-signal IC development tool · EDA · US · founded 2018

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