Digital IC Design Lead (PMIC & Mixed-Signal)
RTL / HDLCompilersFirmwarePhysical designPosted Oct 20, 2026
Overview
Skills named in this posting
- SystemVerilog
- Verilog
- Logic synthesis
- STA
- DFT
- Mixed-signal
- Microarchitecture
- I2C / UART
Summary
As the Digital Design Lead, you will be responsible for the digital architecture, RTL implementation, and system integration of Power Management ICs.
Key Responsibilities
• Digital Architecture: Define and document the micro-architecture for PMIC digital cores, including state machines for complex power-up/down sequencing and fault handling.
• Mixed-Signal Integration: Lead the "digital-on-top" or "analog-on-top" integration, working closely with analog leads to define interfaces and digital control loops.
• RTL Design & Implementation: Design high-quality, low-power RTL using SystemVerilog or Verilog for functions like PWM controllers, serial interfaces (I2C, SPI, PMBus, I3C), and OTP/MTP memory controllers.
• Design for Test (DFT): Oversee the insertion of scan chains, ATPG, and BIST to ensure high production yield and test coverage.
• Verification Strategy: Develop verification plans and drive Mixed-Signal simulations (Verilog-AMS/Real Number Modeling) to validate hardware-software interactions.
• Synthesis & Timing: Lead the synthesis, Logic Equivalency Checking (LEC), and Static Timing Analysis (STA) flows to ensure the digital logic meets performance targets across all process corners.
Required Qualifications
• Education: Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• Experience: 10+ years in digital IC design, with at least 5 years focused on PMIC or Mixed-Signal products.
• Technical Expertise:
Proficiency in SystemVerilog/Verilog RTL coding for synthesis.
Hands-on experience with digital control loops for power converters
Familiarity with Cadence (Genus/Tempus) or Synopsys (Design Compiler/PrimeTime) toolsets.
• Process Knowledge: Experience with BCD process nodes and understanding of Clock Domain Crossing (CDC) in mixed-signal environments.
Preferred Skills
• Knowledge of firmware/software interactions for programmable PMICs.
• Proven ability to lead and mentor a team of digital designers through multiple successful tape-outs.
Location: Prefer Santa Clara, CA
Apply on the employer's site
Original posting: celerasemi.com
RISC-V ecosystem
Celera in the RISC-V ecosystem
Automated analog/mixed-signal IC development tool · EDA · US · founded 2018
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