Date posted 10/18/2026 Category Engineering Hire Type Employee Job ID 19267 Remote Eligible No Date Posted 10/18/2026 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to
Physical design jobs 2,034
Physical design, place-and-route, timing closure and backend flows.
Roles 301–330 of 2,034, newest first.
- Yerevan, ArmeniaRTL / HDLVerificationPhysical designOct 19, 2026
- Ho Chi Minh City, VietnamRTL / HDLCompilersPhysical designOct 19, 2026
Alternate Job Titles • Applications Engineer, EDA Tools • Customer Support Engineer, Physical Design • Technical Applications Engineer, ASIC Implementation • Field Applications Engineer, Design Implementation • Solutions Engineer, Physical
- Ho Chi Minh City, VietnamRTL / HDLCompilersPhysical designOct 19, 2026
Alternate Job Titles • Applications Engineer, EDA Tools • Customer Support Engineer, Physical Design • Technical Applications Engineer, ASIC Implementation • Field Applications Engineer, Design Implementation • Solutions Engineer, Physical
- Ho Chi Minh City, VietnamRTL / HDLCompilersPhysical designOct 19, 2026
Alternate Job Titles • Applications Engineer, EDA Tools • Customer Support Engineer, Physical Design • Technical Applications Engineer, ASIC Implementation • Field Applications Engineer, Design Implementation • Solutions Engineer, Physical
Physical design Engineer
NXP Semiconductors Netherlands B.V.
BangaloreRTL / HDLPhysical designOct 18, 2026Generic Job Description (not Job Level specific): The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP, Subsystem or IC design. The individual is responsible from RTL synthesis to GDS implement
- Mountain ViewPhysical designOct 17, 2026
WHAT MATX IS BUILDING MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. ABOUT THE ROLE We are seeking a hands-on Lab Manager t
- Master internship - LeuvenPhysical designOct 17, 2026
Logic synthesis turns a design into gates with cost models that were written for the technologies of the past: a cell costs what its library entry says, and the structure of the circuit below the gate is invisible to the tool. Emerging tran
- Master internship, PhD internship - LeuvenCompilersPhysical designOct 17, 2026
Context Advanced HBM–GPU integration is a key enabler for next-generation AI systems, yet thermal constraints remain a primary limiter. imec has recently demonstrated system-technology co-optimization approaches to mitigate thermal bottlene
Lead Software Engineer
Cadence Design Systems, Inc.
AUSTINPhysical designOct 17, 2026At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. About the Role Join the Innovus team to develop next-generation routing and physical synthesis technologies for digital IC desig
Senior Digital Design Engineer
Analog Devices, Inc.
Germany, Munich, SeidlstrRTL / HDLFirmwarePhysical designOct 17, 2026About Analog Devices Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technolog
Senior Silicon Validation Methodology Engineer - Low Power
NVIDIA Corporation
China, ShanghaiFirmwarePhysical designSoC / ASICOct 17, 2026NVIDIA Silicon Co-Design Group (SCG) is a wide-ranging, multi-functional team at NVIDIA. We sit at the crossroads of design, architecture, marketing, operations, and productization. Our contributions span from the architecture stage through
Deputy Director, Product Platforms
MIPS Tech LLC.
Richardson, Texas, United States of America, Austin, Texas, United States of AmericaRISC-VCompilersKernel / LinuxOct 17, 2026About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global
Sr. Product Development Engineer
Advanced Micro Devices (AMD)
Secaucus, New JerseyPhysical designOct 16, 2026ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for ta
Senior Logic Design Engineer
Microsoft Corporation
United States, Oregon, Hillsboro, United States, Washington, Redmond, United States, California, Mountain View, United States, Texas, Austin, United States, North Carolina, RaleighRTL / HDLPhysical designSoC / ASICOct 16, 2026Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core
Senior Hardware Engineer
Microsoft Corporation
United States, Washington, RedmondRTL / HDLPhysical designOct 16, 2026Overview Microsoft Azure is building a high-performance and reliable public cloud, and we are seeking talented individuals who can navigate the full technology stack—from hardware to systems to applications—turning ideas into production sy
- US-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDGRTL / HDLVerificationFirmwareOct 16, 2026
Date Posted: 2026-10-15 Country: United States of America Location: US-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDG Position Role Type: Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements: The ability to obtai
- US-AZ-TUCSON-M02 ~ 1151 E Hermans Rd ~ BLDG M02RTL / HDLVerificationFirmwareOct 16, 2026
Date Posted: 2026-10-15 Country: United States of America Location: US-AZ-TUCSON-M02 ~ 1151 E Hermans Rd ~ BLDG M02 Position Role Type: Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements: Active and transferable U.S. g
Analog IC Layout Engineer
NXP Semiconductors Netherlands B.V.
GuadalajaraPhysical designOct 16, 2026About the Team NXP Semiconductors is seeking an Analog IC Layout Engineer to join the Central Layout Group serving the Power & Energy Business Line, with a primary focus on Automotive Power Solutions (APS). The Central Layout Group delive
Custom Layout Designer (Analog Layout Designer)
Cadence Design Systems, Inc.
CARYPhysical designOct 16, 2026At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our team of layout designers creating challenging IP designs for the consumer, industrial, and automotive markets. Our desig
Principal Engineer, Edge NPU Engineering
Analog Devices, Inc.
China, Shanghai, Pudong, ZuChongzhiRISC-VRTL / HDLCompilersOct 16, 2026About Analog Devices Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technolog
Emulation Performance/Debug Engineer
Qualcomm Technologies, Inc.
San Diego, California, United States of America, Austin, Texas, United States of America, Folsom, California, United States of America, Hillsboro, Oregon, United States of America, Markham, Ontario, Canada, Santa Clara, California, United States of AmericaRTL / HDLVerificationKernel / LinuxOct 16, 2026Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation exper
Senior Emulation Performance Methodology & Debug Engineer
Qualcomm Technologies, Inc.
San Diego, California, United States of America, Austin, Texas, United States of America, Folsom, California, United States of America, Hillsboro, Oregon, United States of America, Markham, Ontario, Canada, Santa Clara, California, United States of AmericaRTL / HDLVerificationKernel / LinuxOct 16, 2026Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Senior Emulation Performance Methodology & Debug Engineer Minimum Qualifications: Bachelor's degree in Science, En
- Markham, CanadaRTL / HDLVerificationPhysical designOct 16, 2026
Date posted 10.04.2026 Category Engineering Hire Type Employee Job ID 18730 Base Salary Range $146000-$219000 Remote Eligible No Date Posted 10.04.2026 Note: This position is posted for Markham, but it is open to candidates across Ca
ASIC DFT Engineer
Synopsys
Wuhan, ChinaPhysical designSoC / ASICOct 16, 2026Date posted 10.13.2026 Category Engineering Hire Type Employee Job ID 18744 Remote Eligible No Date Posted 10.13.2026 ASIC Design for Test (DFT) Engineer – Job Description We are seeking a highly motivated ASIC DFT Engineer to join o
- Hyderabad, IndiaRTL / HDLPhysical designSoC / ASICOct 16, 2026
Date posted 10.14.2026 Category Engineering Hire Type Employee Job ID 19060 Remote Eligible No Date Posted 10.14.2026 Job Description and Requirements We Are: At Synopsys, we drive the innovations that shape the way we live and conne
RTL Methodology Silicon Design Engineer
Advanced Micro Devices (AMD)
Austin, TexasRTL / HDLVerificationPhysical designOct 15, 2026ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every
- 🇺🇸 Sunnyvale, CAPhysical designSoC / ASICOct 15, 2026
**Job Title** DFT Lead **About the Role** Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We are looking for a DFT Lead to own the test architecture of our m
- 🇺🇸 Sunnyvale, CACompilersPhysical designSoC / ASICOct 15, 2026
**job_title** Physical Design Engineer (PnR) **job_description** **Job Title** Physical Design Engineer (PnR) **About the Role** Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and ph
- 🇺🇸 Sunnyvale, CARTL / HDLCompilersPhysical designOct 15, 2026
**Job Title** Physical Design (PnR) Lead **Job Title** Physical Design (PnR) Lead **About the Role** Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We are
- 🇺🇸 Sunnyvale, CARTL / HDLPhysical designOct 15, 2026
**Job Title** Senior/Principal Analog Mixed-Signal Design Engineer, Optical Receiver **About the Role** Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We ar