Dresden, DE (primary site)2026-10-27
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294 results · page 1 of 12 · dates: UTC
ASIC Engineer, Networking Chip Design - New College Grad 2027
NVIDIA Corporation
China, ShanghaiRTL / HDLVerificationSoC / ASIC2026-10-26Senior Chip Design Verification Engineer
NVIDIA Corporation
Israel, Tel AvivRTL / HDLVerificationFirmwareSoC / ASIC2026-10-26Chip Design Integration Engineer
International Business Machines Corporation
Bangalore, IN2026-10-26- Austin, TX2026-10-22
Analog Circuit Design Engineer – New Grad
MediaTek Inc
Austin, TXVerificationSoC / ASIC2026-10-213DIC Memory DTCO Engineer
MediaTek Inc
San Jose, CACompilersFirmwarePhysical designSoC / ASIC2026-10-20VLSI Design Engineer
Retym
2026-10-20- Physical design2026-10-20
Senior Software Engineer
RaiderChip
On-Site (Solares, Spain) • Full-timeRequirements: • Mandatory expert-level Python and C • Minimum 8 years of professional software development experience • Design, implement, and maintain high-quality software components • Write efficient, clean, and maintainable code • Collaborate with hardware and systems teams • Ability to work independently and deliver reliably2026-10-20Software Team Lead
RaiderChip
On-Site (Solares, Spain) • Full-timeRequirements: • Mandatory expert-level Python and C • Senior profile with >10 years of professional software experience • Lead and mentor a team of software engineers • Maintain hands-on involvement in coding and architecture • Enforce code quality, best practices, and technical standards • Review designs, pull requests, and critical implementations • Proven ability to balance leadership and deep technical work2026-10-20ASIC Backend Engineer
RaiderChip
On-Site (Solares, Spain) • Full-timeRequirements: • Own the technical oversight of ASIC back-end executed by design service partners • Review, challenge, and validate P&R, timing closure, DRC/LVS, and sign-off results • Define and review backend constraints and deliverables • Strong understanding of physical design flows and trade-offs • Working experience with Synopsys tools • Proven experience with full ASIC tapeouts (strong plus)SoC / ASIC2026-10-20ASIC Verification Engineer
RaiderChip
On-Site (Solares, Spain) • Full-timeRequirements: • Develop and execute comprehensive verification strategies for ASIC designs • Create simulation environments to aggressively validate functionality • Leverage existing FPGA-proven designs as reference and validation baseline • Strong experience with RTL simulation and verification methodologies • Working experience with Synopsys toolsVerificationSoC / ASIC2026-10-20FPGA Engineer (Prototyping)
RaiderChip
On-Site (Solares, Spain) • Full-timeRequirements: • Use FPGA emulation to stress, debug, and validate ASIC-designs • Leverage long-running, proven FPGA prototypes as functional reference • Validate functionality through SW simulation and HW emulation • Collaborate closely with ASIC frontend and verification engineers • Drive issue detection, root-cause analysis, and fix validation • Strong experience with RTL simulation and FPGA toolchains (AMD/Xilinx)FPGA2026-10-20Package Design Engineers
Chipletz
2026-10-20- Palo Alto OfficeRTL / HDLPhysical designSoC / ASIC2026-10-19
- Palo Alto OfficeRTL / HDLVerificationPhysical designSoC / ASIC2026-10-19
Physical Design Engineer
VoltAI
Palo Alto OfficeCompilersPhysical design2026-10-19RTL Design Engineer
VoltAI
Palo Alto OfficeRTL / HDLVerificationPhysical design2026-10-19- Austin, TX2026-10-19
Senior Chip Design Verification Engineer
NVIDIA Corporation
Israel, Yokneam, Israel, Tel AvivRTL / HDLVerificationFirmwareSoC / ASIC2026-10-13[2027 Campus Hire] System Application Engineer
MediaTek Inc
Singapore2026-10-12Senior RF/mmWave IC Design Engineer
MediaTek Inc
Cambourne2026-10-08- San Diego, CARTL / HDLCompilersPhysical designSoC / ASIC2026-10-08
Physical Design Senior Engineer
OpenChip
Roma, ItalyRISC-VRTL / HDLPhysical designSoC / ASIC2026-10-08
