Front-End Design Engineer
Synopsys
Hillsboro, OregonRTL / HDLVerificationCompilersSoC / ASIC2026-11-14
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23 results · dates: UTC
- Sunnyvale, CaliforniaRTL / HDLVerificationCompilersSoC / ASIC2026-11-12
- Cambridge, England, United KingdomRISC-VRTL / HDLVerificationCompilers2026-11-05
- Arlington, VA, United States2026-11-04
- Sunnyvale, CaliforniaRTL / HDLVerificationCompilersSoC / ASIC2026-10-22
FPGA Engineer (Prototyping)
RaiderChip
On-Site (Solares, Spain) • Full-timeRequirements: • Use FPGA emulation to stress, debug, and validate ASIC-designs • Leverage long-running, proven FPGA prototypes as functional reference • Validate functionality through SW simulation and HW emulation • Collaborate closely with ASIC frontend and verification engineers • Drive issue detection, root-cause analysis, and fix validation • Strong experience with RTL simulation and FPGA toolchains (AMD/Xilinx)FPGA2026-10-20Group Director, Design Engineering - Front End
Cadence Design Systems, Inc.
AUSTINRTL / HDLVerificationFirmwarePhysical design2026-10-07Senior Engineer, Digital IC Design
STMicroelectronics International N.V.
SingaporeRTL / HDLFirmwarePhysical designSoC / ASIC2026-09-23- HsinChuVerification2026-09-22
Lead FrontEnd Methodology Engineer
Cadence Design Systems, Inc.
BANGALORERTL / HDLVerification2026-09-21Frontend Engineer
Cadence Design Systems, Inc.
SHANGHAIRTL / HDLPhysical design2026-09-21CDI - Senior SoC Digital Design Engineer – Digital Image Sensor F/H
STMicroelectronics International N.V.
Paris, FranceRTL / HDLVerificationFirmwareSoC / ASIC2026-09-15CDI - Senior SoC Digital Design Engineer – Digital Mixed-Signal IC F/H
STMicroelectronics International N.V.
Grenoble, FranceRTL / HDLSoC / ASIC2026-09-15Front End Design Verification Engineer
Tenstorrent
Santa Clara, California, United States; SpainRISC-VRTL / HDLVerificationCompilers2026-09-15Lead RTL Design Engineer
STMicroelectronics International N.V.
Bangalore, IndiaRTL / HDLPhysical designSoC / ASIC2026-09-11Physical Design Engineer - Frontend
Rebellions
RTL / HDLPhysical design2026-08-30- Santa Clara, California, United StatesRISC-VRTL / HDLVerificationCompilers2026-07-31
- Austin, Texas, United StatesRISC-VRTL / HDLVerificationCompilers2026-07-31
Senior Engineer, Analog/Mixed-Signal Design
STMicroelectronics International N.V.
Singapore, Singapore2026-07-21Internship: Analog Design Engineer
STMicroelectronics International N.V.
Pisa, Italy2026-07-15Product Line Director, Frontend RCA & Coverage
Alpha Design AI
San JoseRTL / HDLVerificationSoC / ASIC2026-07-10Senior ASIC (Front End) Design Engineer
Ethernovia
Toronto - HybridRTL / HDLVerificationPhysical designSoC / ASIC2024-10-04Senior ASIC (Front-End) Design Engineer
Ethernovia
San Jose, CARTL / HDLVerificationPhysical designSoC / ASIC2024-10-04
