Physical design, place-and-route, timing closure and backend flows.
Roles 241–270 of 2,034, newest first.
Nordic Semiconductor ASA
About the job As a ASIC RTL Design Engineer at Nordic Semiconductor, you will play an important role in developing the next generation of cutting-edge Wi-Fi SoCs that power connected devices around the world. You will be working on digital
Nordic Semiconductor ASA
About the job In this job you will play a key role in developing the next generation of advanced semiconductor solutions, taking ideas from architecture and specification through transistor-level CMOS design, verification, and chip integra
Mobilint
Role Summary 고성능·저전력 AI 반도체를 위한 NPU Architect는 차세대 AI Workload의 연산 특성을 정량적으로 분석하고, 이를 최적으로 수용하는 NPU Architecture를 정의하는 역할을 수행합니다. Compute Datapath, Memory Hierarchy, Interconnect, ISA에 이르는 NPU 전반의 구조를 설계하며, PPA(Performanc
Mobilint
Role Summary NPU RTL Engineer는 NPU의 핵심 Datapath 및 Control Logic을 설계하고, PPA(Performance/Power/Area) 목표를 충족하는 합성 가능한 고품질 RTL을 구현합니다. Architecture, DV, Physical Design 등 다양한 직군과 협업하며, RTL 작성 단계부터 Synthesis, Timing Closure,
Mobilint
Role Summary 고성능·저전력 AI 반도체의 시스템 설계를 총괄하는 SoC Architect는 NPU를 포함한 AP, DDR, Bus, PCIe, USB, Camera, Display 등 SoC 전체 아키텍처를 정의하고, Compute-Memory-Bus 구조를 통합적으로 설계합니다. 다양한 시스템 구성 요소를 유기적으로 연결하고 Software Stack과의 Co-design을 통
Role Summary “다음 AI Chip은 어떤 Chip이어야 하는가?” 이 질문에 답하고, 그 답을 실제 Silicon으로 만들어낼 인재를 찾습니다. AI SoC Product Architect / Product Planning은 Target Application과 AI Workload를 바탕으로 AI 반도체를 정의하고, 실제 Silicon으로 구현되기까지 제품 전반의 기술적 의사결
About the role • We are seeking an experienced Front-end Digital Design Engineer to join our Sunnyvale based team. The ideal candidate will have a strong background in Embedded and Mixedmode SoC architectures, Verilog, and Synthesis in dee
About the role • We are seeking an experienced Package Substrate Design Engineer to join us and own package and substrate design for the chips and multi-die modules at the heart of Lyte’s fully vertically integrated 4D FMCW LiDAR platform -
Position Overview MangoBoost is actively seeking for highly skilled and motivated IP Design Engineers to join our hardware development group. We are recruiting across multiple specialization tracks — Digital Hardware IP Des
Position Overview MangoBoost is actively seeking a highly skilled and motivated FPGA Engineer to join our Hardware Development Group. In this role, you will be responsible for FPGA IP integration, synthesis, timing closure
Maven Silicon Softech Private Limited
Open positions : 6 Experience : 3-8 years Education : M.Tech VLSI/BE ECE Industry Type : Education/E-Learning/Semiconductor Job Type : Training Job Description • Extensive hands on and teaching experience on Digital/SV/UVM/Verilog/VHD
Alternate Job Titles • Applications Engineer, EDA Tools • Customer Support Engineer, Physical Design • Technical Applications Engineer, ASIC Implementation • Field Applications Engineer, Design Implementation • Solutions Engineer, Physical
Alternate Job Titles • Applications Engineer, EDA Tools • Customer Support Engineer, Physical Design • Technical Applications Engineer, ASIC Implementation • Field Applications Engineer, Design Implementation • Solutions Engineer, Physical
International Business Machines Corporation
Physical design team is responsible for designing high performance microprocessor blocks for IBM Power and z mainframe servers. As a Hardware Developer at IBM, you'll get to work on the systems that are driving the quantum revolution and th
International Business Machines Corporation
At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance,
Generation Alpha Transistor
GenAlpha ← All open roles Member of Technical Staff — Analog IC Headquartered in San FranciscoEngineeringFull-time GenAlpha brings AI to silicon’s toughest challenges. We’re an early-stage startup, founded in 2024 by experts in semicond
Generation Alpha Transistor
GenAlpha ← All open roles Member of Technical Staff — AI for Silicon Headquartered in San FranciscoEngineeringFull-time GenAlpha brings AI to silicon’s toughest challenges. We’re an early-stage startup, founded in 2024 by experts in sem
Senior Staff Software Engineer – Placement / Routing / Physical Synthesis Location: Toronto, Canada We are looking for an experienced software engineer to work in the Efinity Place & Route team. Develop state-of-the-art techniques for pla
Efinix Inc
Digital IP Engineer Location: Penang, Malaysia Responsibilities: • Work on the digital IP and/or it’s subsystem definition and development covering RTL creation, verification, and documentation for the IP and system developed. The IP cou
Efinix Inc
Physical Design Engineer Location: Penang, Malaysia Responsibilities: • Implement all physical design related aspects from power distribution planning; Placement and optimization (timing/area/power); Clock network planning; Clock tree sy
Efinix Inc
System Solutions FPGA Engineer Location: Penang, Malaysia Responsibilities: • Design and develop RTL (Verilog/SystemVerilog) for FPGA-based systems. • Integrate and validate RISC-V cores and SoC IP components (e.g., interconnects, perip
About EdgeQ EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress
About EdgeQ EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress
About EdgeQ EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress
About EdgeQ EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress
About EdgeQ EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress
Summary As the Digital Design Lead, you will be responsible for the digital architecture, RTL implementation, and system integration of Power Management ICs. Key Responsibilities • Digital Architecture: Define and document the micro-arch
Description Ingénieur Sécurité Fonctionnelle (H/F) Localisation : Sophia Antipolis , France Arteris connecte l’innovation Notre technologie aide les entreprises les plus visionnaires au monde — des startups aux leaders du Fortune 500 à
Description Staff Product Engineer (H/F) Localisation : Montigny-le-Bretonneux (78), France Arteris connecte l’innovation Arteris permet aux équipes d’ingénierie et de conception des entreprises les plus innovantes au monde de connecter
Description Principal Hardware Architect (H/F)Localisation : Sophia Antipolis France Arteris connecte l’innovationNotre technologie aide les entreprises les plus visionnaires au monde — des startups aux leaders du Fortune 500 à concevoir d
